#!/bin/tcsh -f

  ###
  ### 
  ###

  ### USAGE:  ./compile_top_cache.sh
  ###         OR
  ###         source compile_top_cache.sh


  which vsim >& /dev/null
  if ( $status != 0 ) then
    printf "\n\n  ERROR: Modelsim not found\n\n"
    exit;
  endif


  if ( ! (-e  libraries/) ) then
    vlib           ./libraries/ ;
    vlib           ./libraries/work/ ;
    vmap  work     ./libraries/work/ ;
  endif

  set hdl_root   = ../rtl

  set opt   = "-93 -nologo -quiet -lint -check_synthesis"
  set opttb = "-93 -nologo -quiet -lint"


  # - - - - - - - - - - - - - - START RISCV CPU - - - - - - - - - - - - - -
  printf "                                                               \n"
  printf " COMPILING RISCV CPU:                                          \n"
  printf "   rv_pkg               (configuration/parameters file)        \n"
  printf "   rv_cpu                :  /u_cpu                             \n"
  printf "   |--rv_fetch           :  /u_core/u_fetch                    \n"
  printf "   |--rv_decode          :  /u_core/u_decode                   \n"
  printf "   |   |--rv_decoder     :  /u_core/u_decode/u_dec             \n"
  printf "   |--rv_issue           :  /u_core/u_issue                    \n"
  printf "   |   |--rv_pipe_ctrl   :  /u_core/u_issue/u_pipe_ctrl        \n"
  printf "   |   |--rv_regfile     :  /u_core/u_issue/u_regfile          \n"
  printf "   |--rv_exec            :  /u_core/u_exec                     \n"
  printf "   |   |--rv_alu         :  /u_core/u_exec/u_alu               \n"
  printf "   |   |--rv_multiplier  :  /u_core/u_exec/u_mul               \n"
  printf "   |   |--rv_divider     :  /u_core/u_exec/u_div               \n"
  printf "   |--rv_lsu             :  /u_core/u_lsu                      \n"
  printf "   |-- |-rv_lsu_fifo     :  /u_core/u_lsu/u_lsu_request        \n"
  printf "   |--rv_csr             :  /u_core/u_csr                      \n"
  printf "   |   |--rv_csr_rf      :  /u_core/u_csr/u_csr_rf             \n"
  printf "   |--rv_mmu             :  /u_core/u_mmu                      \n"
  printf "                                                               \n"

  vcom ${opt} -work work $hdl_root/core/rv_pkg.vhd

  vcom ${opt} -work work $hdl_root/core/rv_fetch.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_decoder.vhd
  vcom ${opt} -work work $hdl_root/core/rv_decode.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_multiplier.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_divider.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_alu.vhd
  vcom ${opt} -work work $hdl_root/core/rv_exec.vhd

  vcom ${opt} -work work    $hdl_root/core/rv_pipe_ctrl.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_regfile.vhd
  vcom ${opt} -work work $hdl_root/core/rv_issue.vhd

  vcom ${opt} -work work    $hdl_root/core/rv_csr_rf.vhd
  vcom ${opt} -work work $hdl_root/core/rv_csr.vhd
  vcom ${opt} -work work $hdl_root/core/rv_lsu.vhd

  vcom ${opt} -work work $hdl_root/core/rv_mmu.vhd

  vcom ${opt} -work work $hdl_root/core/rv_cpu.vhd
  # - - - - - - - - - - - - - - END RISCV CPU - - - - - - - - - - - - - -




  # - - - - - - - - - - - - - START RISCV SOC TCM - - - - - - - - - - - - -
  printf "                                                               \n"
  printf " COMPILING RISCV SOC TCM                                       \n"
  printf "                                                               \n"
  printf " rv_soc_tcm ( ! set CLK_FREQ and UART_SPEED, default 50M/1M !  \n"
  printf "   |                                                           \n"
  printf "   |--dbg_bridge     :  /u_dbg_bridge                          \n"
  printf "   |--vsperips       :  /u_vsperips                            \n"
  printf "   |--rv_tcm         :  /u_rv_tcm                              \n"
  printf "   |  |  ( ! select extensions and tcm ram size 1K - 1M ! )    \n"
  printf "      |--rv_cpu      :  /u_rv_tcm/u_cpu                        \n"
  printf "      |--tcm_mem     :  /u_rv_tcm/u_tcm_mem                    \n"
  printf "         |--tcm_axi  :  /u_rv_tcm/u_tcm_mem/u_tcm_axi          \n"
  printf "                                                               \n"
  printf "                                                               \n"

  vcom ${opt} -work work  $hdl_root/soc/vsgpio.vhd
  vcom ${opt} -work work  $hdl_root/soc/vsspi_lite.vhd
  vcom ${opt} -work work  $hdl_root/soc/vsuart_lite.vhd
  vcom ${opt} -work work  $hdl_root/soc/vstimer.vhd
  vcom ${opt} -work work  $hdl_root/soc/vsirq_ctrl.vhd
  vcom ${opt} -work work  $hdl_root/soc/rv_if.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_pkg.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_tfifo.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_rfifo.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_transmitter.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_receiver.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart16550.vhd

  vcom ${opt} -work work  $hdl_root/soc/vsperips.vhd

  vcom ${opt} -work work  $hdl_root/top_cache/axi4_arb.vhd
  vcom ${opt} -work work  $hdl_root/top_cache/axi4_retime.vhd
  vcom ${opt} -work work  $hdl_root/top_cache/axi_mem_if.vhd

  vcom ${opt} -work work  $hdl_root/dbg/dbg_bridge_fifo.vhd
  vcom ${opt} -work work  $hdl_root/dbg/dbg_bridge_uart.vhd
  vcom ${opt} -work work  $hdl_root/dbg/dbg_bridge.vhd

  vcom ${opt} -work work  $hdl_root/top_tcm/tcm_axi.vhd
  vcom ${opt} -work work  $hdl_root/top_tcm/tcm_mem.vhd
  vcom ${opt} -work work  $hdl_root/top_tcm/rv_tcm.vhd

  vcom ${opt} -work work  $hdl_root/soc/rv_soc_tcm.vhd
  # - - - - - - - - - - - - - END RISCV SOC TCM - - - - - - - - - - - - -



  printf '  - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\n'
  printf '                                                                 \n'
  printf '   UART upload (short loop) and boot :                           \n'
  printf '     vsim -lib work rv_soc_tcm -do soc_tcm.do &                  \n'
  printf '                                                                 \n'
  printf '                                                                 \n'
  printf '   OR boot only (no software):                                   \n'
  printf '                                                                 \n'
  printf '   vsim -lib work rv_soc_tcm -do "add wave rv_soc_tcm/*"         \n'
  printf '     In vsim window:                                             \n'
  printf '     #  add wave /rv_soc_tcm/u_rv_tcm/u_cpu/xrst_i               \n'
  printf '     #  add wave /rv_soc_tcm/u_rv_tcm/u_cpu/imem_*               \n'
  printf '     #  add wave /rv_soc_tcm/u_rv_tcm/u_cpu/dmem_*               \n'
  printf '     restart -f ;                                                \n'
  printf '     force -freeze  /rv_soc_tcm/xrst_i 0 0 ;                     \n'
  printf '     force -freeze  /rv_soc_tcm/clk_i 1 0, 0 {10 ns} -r {20 ns} ;\n'
  printf '     force -freeze  /rv_soc_tcm/uart_txd_i 1 0 ;                 \n'
  printf '     force -freeze  /rv_soc_tcm/uart2_txd_i 1 0 ;                \n'
  printf '     force -freeze  /rv_soc_tcm/spi_miso_i  1 0 ;                \n'
  printf '     force -freeze  /rv_soc_tcm/gpio_i 00 0                      \n'
  printf '     run 1 us ;                                                  \n'
  printf '     force -freeze  /rv_soc_tcm/xrst_i 1 0 ;                     \n'
  printf '     run 1 us ;                                                  \n'
  printf '     ###   release core reset                                    \n'
  printf '     force -freeze  /rv_soc_tcm/rv_core_ena_w 1 0 ;              \n'
  printf '     run 1 us ;                                                  \n'
  printf '                                                                 \n'
  printf '  - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\n'
  printf '\n'

