-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--
-- Copyright 2025 VLSI Solution Oy
-- SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
--
-- Licensed under the Solderpad Hardware License v 2.1 (the "License");
-- you may not use this file except in compliance with the License, or,
-- at your option, the Apache License version 2.0.
-- You may obtain a copy of the License at
--
--    https://solderpad.org/licenses/SHL-2.1/
--
-- Unless required by applicable law or agreed to in writing, any work
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
--                               RISCV core
--                                 V1.1
--
--
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

-- - - - - - - -
--  libraries
-- - - - - - - -
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.rv_pkg.all;


entity axi_mem_if is
  generic ( AXIDATA_W  : natural range 32 to 64 := 32 );         -- select 32/64
  port ( clk_i             : in  std_logic;
         xrst_i            : in  std_logic;                      -- syncr reset
         --
         axi_a_awvalid_i  : in  std_logic;                       -- dbg uart
         axi_a_awaddr_i   : in  slv_31_00;
         axi_a_awid_i     : in  slv_03_00;                       --    X"0"
         axi_a_awlen_i    : in  slv_07_00;                       --    X"00"
         axi_a_awburst_i  : in  slv_01_00;                       --    "01"
         axi_a_wvalid_i   : in  std_logic;
         axi_a_wdata_i    : in  slv_t(AXIDATA_W-1 downto 0);
         axi_a_wstrb_i    : in  slv_t(AXIDATA_W/8-1 downto 0);   -- 64b / 32b
         axi_a_wlast_i    : in  std_logic;                       --    '1'
         axi_a_bready_i   : in  std_logic;
         axi_a_arvalid_i  : in  std_logic;
         axi_a_araddr_i   : in  slv_31_00;
         axi_a_arid_i     : in  slv_03_00;                       --    X"0"
         axi_a_arlen_i    : in  slv_07_00;                       --    X"00"
         axi_a_arburst_i  : in  slv_01_00;                       --    "01"
         axi_a_rready_i   : in  std_logic;
         axi_a_awready_o  : out std_logic;
         axi_a_wready_o   : out std_logic;
         axi_a_bvalid_o   : out std_logic;
         axi_a_bresp_o    : out slv_01_00;
         axi_a_bid_o      : out slv_03_00;
         axi_a_arready_o  : out std_logic;
         axi_a_rvalid_o   : out std_logic;
         axi_a_rdata_o    : out slv_t(AXIDATA_W-1 downto 0);
         axi_a_rresp_o    : out slv_01_00;
         axi_a_rid_o      : out slv_03_00;
         axi_a_rlast_o    : out std_logic;
         --
         axi_b_awvalid_i   : in  std_logic;                      -- NC
         axi_b_awaddr_i    : in  slv_31_00;
         axi_b_awid_i      : in  slv_03_00;
         axi_b_awlen_i     : in  slv_07_00;
         axi_b_awburst_i   : in  slv_01_00;
         axi_b_wvalid_i    : in  std_logic;
         axi_b_wdata_i     : in  slv_t(AXIDATA_W-1 downto 0);
         axi_b_wstrb_i     : in  slv_t(AXIDATA_W/8-1 downto 0);  -- 64b / 32b
         axi_b_wlast_i     : in  std_logic;
         axi_b_bready_i    : in  std_logic;
         axi_b_arvalid_i   : in  std_logic;
         axi_b_araddr_i    : in  slv_31_00;
         axi_b_arid_i      : in  slv_03_00;
         axi_b_arlen_i     : in  slv_07_00;
         axi_b_arburst_i   : in  slv_01_00;
         axi_b_rready_i    : in  std_logic;
         axi_b_awready_o   : out std_logic;
         axi_b_wready_o    : out std_logic;
         axi_b_bvalid_o    : out std_logic;
         axi_b_bresp_o     : out slv_01_00;
         axi_b_bid_o       : out slv_03_00;
         axi_b_arready_o   : out std_logic;
         axi_b_rvalid_o    : out std_logic;
         axi_b_rdata_o     : out slv_t(AXIDATA_W-1 downto 0);
         axi_b_rresp_o     : out slv_01_00;
         axi_b_rid_o       : out slv_03_00;
         axi_b_rlast_o     : out std_logic;
         --
         axi_c_awvalid_i   : in  std_logic;                      -- cpu
         axi_c_awaddr_i    : in  slv_31_00;
         axi_c_awid_i      : in  slv_03_00;
         axi_c_awlen_i     : in  slv_07_00;
         axi_c_awburst_i   : in  slv_01_00;
         axi_c_wvalid_i    : in  std_logic;
         axi_c_wdata_i     : in  slv_t(AXIDATA_W-1 downto 0);
         axi_c_wstrb_i     : in  slv_t(AXIDATA_W/8-1 downto 0);  -- 64b / 32b
         axi_c_wlast_i     : in  std_logic;
         axi_c_bready_i    : in  std_logic;
         axi_c_arvalid_i   : in  std_logic;
         axi_c_araddr_i    : in  slv_31_00;
         axi_c_arid_i      : in  slv_03_00;
         axi_c_arlen_i     : in  slv_07_00;
         axi_c_arburst_i   : in  slv_01_00;
         axi_c_rready_i    : in  std_logic;
         axi_c_awready_o   : out std_logic;
         axi_c_wready_o    : out std_logic;
         axi_c_bvalid_o    : out std_logic;
         axi_c_bresp_o     : out slv_01_00;
         axi_c_bid_o       : out slv_03_00;
         axi_c_arready_o   : out std_logic;
         axi_c_rvalid_o    : out std_logic;
         axi_c_rdata_o     : out slv_t(AXIDATA_W-1 downto 0);
         axi_c_rresp_o     : out slv_01_00;
         axi_c_rid_o       : out slv_03_00;
         axi_c_rlast_o     : out std_logic;
         --
         xmem_awready_i    : in  std_logic;                      -- xmem
         xmem_wready_i     : in  std_logic;
         xmem_bvalid_i     : in  std_logic;
         xmem_bresp_i      : in  slv_01_00;
         xmem_bid_i        : in  slv_03_00;                      -- NC
         xmem_arready_i    : in  std_logic;
         xmem_rvalid_i     : in  std_logic;
         xmem_rdata_i      : in  slv_t(AXIDATA_W-1 downto 0);
         xmem_rresp_i      : in  slv_01_00;
         xmem_rid_i        : in  slv_03_00;                      -- NC
         xmem_rlast_i      : in  std_logic;                      -- NC
         xmem_awvalid_o    : out std_logic;
         xmem_awaddr_o     : out slv_31_00;
         xmem_awid_o       : out slv_03_00;
         xmem_awlen_o      : out slv_07_00;
         xmem_awburst_o    : out slv_01_00;
         xmem_wvalid_o     : out std_logic;
         xmem_wdata_o      : out slv_t(AXIDATA_W-1 downto 0);
         xmem_wstrb_o      : out slv_t(AXIDATA_W/8-1 downto 0);  -- 64b / 32b
         xmem_wlast_o      : out std_logic;
         xmem_bready_o     : out std_logic;
         xmem_arvalid_o    : out std_logic;
         xmem_araddr_o     : out slv_31_00;
         xmem_arid_o       : out slv_03_00;
         xmem_arlen_o      : out slv_07_00;
         xmem_arburst_o    : out slv_01_00;
         xmem_rready_o     : out std_logic
         );
end entity axi_mem_if;


architecture rtl of axi_mem_if is

  component axi4_arb
    generic ( AXIDATA_W  : natural := 32 );                      -- select 32/64
    port ( clk_i              : in  std_logic;
           xrst_i             : in  std_logic;
           --
           axi_a_awvalid_i    : in  std_logic;                   -- dbg uart
           axi_a_awaddr_i     : in  slv_31_00;
           axi_a_awid_i       : in  slv_03_00;
           axi_a_awlen_i      : in  slv_07_00;
           axi_a_awburst_i    : in  slv_01_00;
           axi_a_wvalid_i     : in  std_logic;
           axi_a_wdata_i      : in  slv_t(AXIDATA_W-1 downto 0);
           axi_a_wstrb_i      : in  slv_t(AXIDATA_W/8-1 downto 0);
           axi_a_wlast_i      : in  std_logic;
           axi_a_bready_i     : in  std_logic;
           axi_a_arvalid_i    : in  std_logic;
           axi_a_araddr_i     : in  slv_31_00;
           axi_a_arid_i       : in  slv_03_00;
           axi_a_arlen_i      : in  slv_07_00;
           axi_a_arburst_i    : in  slv_01_00;
           axi_a_rready_i     : in  std_logic;
           axi_a_awready_o    : out std_logic;
           axi_a_wready_o     : out std_logic;
           axi_a_bvalid_o     : out std_logic;
           axi_a_bresp_o      : out slv_01_00;
           axi_a_bid_o        : out slv_03_00;
           axi_a_arready_o    : out std_logic;
           axi_a_rvalid_o     : out std_logic;
           axi_a_rdata_o      : out slv_t(AXIDATA_W-1 downto 0);
           axi_a_rresp_o      : out slv_01_00;
           axi_a_rid_o        : out slv_03_00;
           axi_a_rlast_o      : out std_logic;
           --
           axi_b_awvalid_i    : in  std_logic;                   -- NC
           axi_b_awaddr_i     : in  slv_31_00;
           axi_b_awid_i       : in  slv_03_00;
           axi_b_awlen_i      : in  slv_07_00;
           axi_b_awburst_i    : in  slv_01_00;
           axi_b_wvalid_i     : in  std_logic;
           axi_b_wdata_i      : in  slv_t(AXIDATA_W-1 downto 0);
           axi_b_wstrb_i      : in  slv_t(AXIDATA_W/8-1 downto 0);
           axi_b_wlast_i      : in  std_logic;
           axi_b_bready_i     : in  std_logic;
           axi_b_arvalid_i    : in  std_logic;
           axi_b_araddr_i     : in  slv_31_00;
           axi_b_arid_i       : in  slv_03_00;
           axi_b_arlen_i      : in  slv_07_00;
           axi_b_arburst_i    : in  slv_01_00;
           axi_b_rready_i     : in  std_logic;
           axi_b_awready_o    : out std_logic;
           axi_b_wready_o     : out std_logic;
           axi_b_bvalid_o     : out std_logic;
           axi_b_bresp_o      : out slv_01_00;
           axi_b_bid_o        : out slv_03_00;
           axi_b_arready_o    : out std_logic;
           axi_b_rvalid_o     : out std_logic;
           axi_b_rdata_o      : out slv_t(AXIDATA_W-1 downto 0);
           axi_b_rresp_o      : out slv_01_00;
           axi_b_rid_o        : out slv_03_00;
           axi_b_rlast_o      : out std_logic;
           --
           axi_c_awvalid_i    : in  std_logic;                   -- cpu
           axi_c_awaddr_i     : in  slv_31_00;
           axi_c_awid_i       : in  slv_03_00;
           axi_c_awlen_i      : in  slv_07_00;
           axi_c_awburst_i    : in  slv_01_00;
           axi_c_wvalid_i     : in  std_logic;
           axi_c_wdata_i      : in  slv_t(AXIDATA_W-1 downto 0);
           axi_c_wstrb_i      : in  slv_t(AXIDATA_W/8-1 downto 0);
           axi_c_wlast_i      : in  std_logic;
           axi_c_bready_i     : in  std_logic;
           axi_c_arvalid_i    : in  std_logic;
           axi_c_araddr_i     : in  slv_31_00;
           axi_c_arid_i       : in  slv_03_00;
           axi_c_arlen_i      : in  slv_07_00;
           axi_c_arburst_i    : in  slv_01_00;
           axi_c_rready_i     : in  std_logic;
           axi_c_awready_o    : out std_logic;
           axi_c_wready_o     : out std_logic;
           axi_c_bvalid_o     : out std_logic;
           axi_c_bresp_o      : out slv_01_00;
           axi_c_bid_o        : out slv_03_00;
           axi_c_arready_o    : out std_logic;
           axi_c_rvalid_o     : out std_logic;
           axi_c_rdata_o      : out slv_t(AXIDATA_W-1 downto 0);
           axi_c_rresp_o      : out slv_01_00;
           axi_c_rid_o        : out slv_03_00;
           axi_c_rlast_o      : out std_logic;
           --
           outport_awready_i  : in  std_logic;                   -- xmem
           outport_wready_i   : in  std_logic;
           outport_bvalid_i   : in  std_logic;
           outport_bresp_i    : in  slv_01_00;
           outport_bid_i      : in  slv_03_00;
           outport_arready_i  : in  std_logic;
           outport_rvalid_i   : in  std_logic;
           outport_rdata_i    : in  slv_t(AXIDATA_W-1 downto 0);
           outport_rresp_i    : in  slv_01_00;
           outport_rid_i      : in  slv_03_00;
           outport_rlast_i    : in  std_logic;
           outport_awvalid_o  : out std_logic;
           outport_awaddr_o   : out slv_31_00;
           outport_awid_o     : out slv_03_00;
           outport_awlen_o    : out slv_07_00;
           outport_awburst_o  : out slv_01_00;
           outport_wvalid_o   : out std_logic;
           outport_wdata_o    : out slv_t(AXIDATA_W-1 downto 0);
           outport_wstrb_o    : out slv_t(AXIDATA_W/8-1 downto 0);
           outport_wlast_o    : out std_logic;
           outport_bready_o   : out std_logic;
           outport_arvalid_o  : out std_logic;
           outport_araddr_o   : out slv_31_00;
           outport_arid_o     : out slv_03_00;
           outport_arlen_o    : out slv_07_00;
           outport_arburst_o  : out slv_01_00;
           outport_rready_o   : out std_logic );
  end component;


  component axi4_retime
    generic ( AXIDATA_W  : natural := 32 );                      -- select 32/64
    port ( clk_i              : in  std_logic;
           xrst_i             : in  std_logic;
           --
           inport_awvalid_i   : in  std_logic;
           inport_awaddr_i    : in  slv_31_00;
           inport_awid_i      : in  slv_03_00;
           inport_awlen_i     : in  slv_07_00;
           inport_awburst_i   : in  slv_01_00;
           inport_wvalid_i    : in  std_logic;
           inport_wdata_i     : in  slv_t(AXIDATA_W-1 downto 0);
           inport_wstrb_i     : in  slv_t(AXIDATA_W/8-1 downto 0);
           inport_wlast_i     : in  std_logic;
           inport_bready_i    : in  std_logic;
           inport_arvalid_i   : in  std_logic;
           inport_araddr_i    : in  slv_31_00;
           inport_arid_i      : in  slv_03_00;
           inport_arlen_i     : in  slv_07_00;
           inport_arburst_i   : in  slv_01_00;
           inport_rready_i    : in  std_logic;
           inport_awready_o   : out std_logic;
           inport_wready_o    : out std_logic;
           inport_bvalid_o    : out std_logic;
           inport_bresp_o     : out slv_01_00;
           inport_bid_o       : out slv_03_00;
           inport_arready_o   : out std_logic;
           inport_rvalid_o    : out std_logic;
           inport_rdata_o     : out slv_t(AXIDATA_W-1 downto 0);
           inport_rresp_o     : out slv_01_00;
           inport_rid_o       : out slv_03_00;
           inport_rlast_o     : out std_logic;
           --
           outport_awready_i  : in  std_logic;
           outport_wready_i   : in  std_logic;
           outport_bvalid_i   : in  std_logic;
           outport_bresp_i    : in  slv_01_00;
           outport_bid_i      : in  slv_03_00;
           outport_arready_i  : in  std_logic;
           outport_rvalid_i   : in  std_logic;
           outport_rdata_i    : in  slv_t(AXIDATA_W-1 downto 0);
           outport_rresp_i    : in  slv_01_00;
           outport_rid_i      : in  slv_03_00;
           outport_rlast_i    : in  std_logic;
           outport_awvalid_o  : out std_logic;
           outport_awaddr_o   : out slv_31_00;
           outport_awid_o     : out slv_03_00;
           outport_awlen_o    : out slv_07_00;
           outport_awburst_o  : out slv_01_00;
           outport_wvalid_o   : out std_logic;
           outport_wdata_o    : out slv_t(AXIDATA_W-1 downto 0);
           outport_wstrb_o    : out slv_t(AXIDATA_W/8-1 downto 0);
           outport_wlast_o    : out std_logic;
           outport_bready_o   : out std_logic;
           outport_arvalid_o  : out std_logic;
           outport_araddr_o   : out slv_31_00;
           outport_arid_o     : out slv_03_00;
           outport_arlen_o    : out slv_07_00;
           outport_arburst_o  : out slv_01_00;
           outport_rready_o   : out std_logic );
  end component;


  signal axi_arb_awvalid_w  : std_logic;
  signal axi_arb_awaddr_w   : slv_31_00;
  signal axi_arb_awid_w     : slv_03_00;
  signal axi_arb_awlen_w    : slv_07_00;
  signal axi_arb_awburst_w  : slv_01_00;
  signal axi_arb_wvalid_w   : std_logic;
  signal axi_arb_wdata_w    : slv_t(AXIDATA_W-1 downto 0);
  signal axi_arb_wstrb_w    : slv_t(AXIDATA_W/8-1 downto 0);     -- 64b / 32b
  signal axi_arb_wlast_w    : std_logic;
  signal axi_arb_bready_w   : std_logic;
  signal axi_arb_arvalid_w  : std_logic;
  signal axi_arb_araddr_w   : slv_31_00;
  signal axi_arb_arid_w     : slv_03_00;
  signal axi_arb_arlen_w    : slv_07_00;
  signal axi_arb_arburst_w  : slv_01_00;
  signal axi_arb_rready_w   : std_logic;
  signal axi_arb_awready_w  : std_logic;
  signal axi_arb_wready_w   : std_logic;
  signal axi_arb_bvalid_w   : std_logic;
  signal axi_arb_bresp_w    : slv_01_00;
  signal axi_arb_bid_w      : slv_03_00;
  signal axi_arb_arready_w  : std_logic;
  signal axi_arb_rvalid_w   : std_logic;
  signal axi_arb_rdata_w    : slv_t(AXIDATA_W-1 downto 0);
  signal axi_arb_rresp_w    : slv_01_00;
  signal axi_arb_rid_w      : slv_03_00;
  signal axi_arb_rlast_w    : std_logic;

begin

  u_arb : axi4_arb
    generic map ( AXIDATA_W  => AXIDATA_W )                      -- select 32/64
    port map ( clk_i              => clk_i,
               xrst_i             => xrst_i,
               --
               axi_a_awvalid_i    => axi_a_awvalid_i,            -- dbg uart
               axi_a_awaddr_i     => axi_a_awaddr_i,
               axi_a_awid_i       => axi_a_awid_i,               --    X"0"
               axi_a_awlen_i      => axi_a_awlen_i,              --    X"00"
               axi_a_awburst_i    => axi_a_awburst_i,            --    "01"
               axi_a_wvalid_i     => axi_a_wvalid_i,
               axi_a_wdata_i      => axi_a_wdata_i,
               axi_a_wstrb_i      => axi_a_wstrb_i,
               axi_a_wlast_i      => axi_a_wlast_i,              --    '1'
               axi_a_bready_i     => axi_a_bready_i,
               axi_a_arvalid_i    => axi_a_arvalid_i,
               axi_a_araddr_i     => axi_a_araddr_i,
               axi_a_arid_i       => axi_a_arid_i,               --    X"0"
               axi_a_arlen_i      => axi_a_arlen_i,              --    X"00"
               axi_a_arburst_i    => axi_a_arburst_i,            --    "01"
               axi_a_rready_i     => axi_a_rready_i,
               axi_a_awready_o    => axi_a_awready_o,
               axi_a_wready_o     => axi_a_wready_o,
               axi_a_bvalid_o     => axi_a_bvalid_o,
               axi_a_bresp_o      => axi_a_bresp_o,
               axi_a_bid_o        => axi_a_bid_o,
               axi_a_arready_o    => axi_a_arready_o,
               axi_a_rvalid_o     => axi_a_rvalid_o,
               axi_a_rdata_o      => axi_a_rdata_o,
               axi_a_rresp_o      => axi_a_rresp_o,
               axi_a_rid_o        => axi_a_rid_o,
               axi_a_rlast_o      => axi_a_rlast_o,
               --
               axi_b_awvalid_i    => axi_b_awvalid_i,            -- NC
               axi_b_awaddr_i     => axi_b_awaddr_i,
               axi_b_awid_i       => axi_b_awid_i,
               axi_b_awlen_i      => axi_b_awlen_i,
               axi_b_awburst_i    => axi_b_awburst_i,
               axi_b_wvalid_i     => axi_b_wvalid_i,
               axi_b_wdata_i      => axi_b_wdata_i,
               axi_b_wstrb_i      => axi_b_wstrb_i,
               axi_b_wlast_i      => axi_b_wlast_i,
               axi_b_bready_i     => axi_b_bready_i,
               axi_b_arvalid_i    => axi_b_arvalid_i,
               axi_b_araddr_i     => axi_b_araddr_i,
               axi_b_arid_i       => axi_b_arid_i,
               axi_b_arlen_i      => axi_b_arlen_i,
               axi_b_arburst_i    => axi_b_arburst_i,
               axi_b_rready_i     => axi_b_rready_i,
               axi_b_awready_o    => axi_b_awready_o,
               axi_b_wready_o     => axi_b_wready_o,
               axi_b_bvalid_o     => axi_b_bvalid_o,
               axi_b_bresp_o      => axi_b_bresp_o,
               axi_b_bid_o        => axi_b_bid_o,
               axi_b_arready_o    => axi_b_arready_o,
               axi_b_rvalid_o     => axi_b_rvalid_o,
               axi_b_rdata_o      => axi_b_rdata_o,
               axi_b_rresp_o      => axi_b_rresp_o,
               axi_b_rid_o        => axi_b_rid_o,
               axi_b_rlast_o      => axi_b_rlast_o,
                --
               axi_c_awvalid_i    => axi_c_awvalid_i,            -- cpu
               axi_c_awaddr_i     => axi_c_awaddr_i,
               axi_c_awid_i       => axi_c_awid_i,
               axi_c_awlen_i      => axi_c_awlen_i,
               axi_c_awburst_i    => axi_c_awburst_i,
               axi_c_wvalid_i     => axi_c_wvalid_i,
               axi_c_wdata_i      => axi_c_wdata_i,
               axi_c_wstrb_i      => axi_c_wstrb_i,
               axi_c_wlast_i      => axi_c_wlast_i,
               axi_c_bready_i     => axi_c_bready_i,
               axi_c_arvalid_i    => axi_c_arvalid_i,
               axi_c_araddr_i     => axi_c_araddr_i,
               axi_c_arid_i       => axi_c_arid_i,
               axi_c_arlen_i      => axi_c_arlen_i,
               axi_c_arburst_i    => axi_c_arburst_i,
               axi_c_rready_i     => axi_c_rready_i,
               axi_c_awready_o    => axi_c_awready_o,
               axi_c_wready_o     => axi_c_wready_o,
               axi_c_bvalid_o     => axi_c_bvalid_o,
               axi_c_bresp_o      => axi_c_bresp_o,
               axi_c_bid_o        => axi_c_bid_o,
               axi_c_arready_o    => axi_c_arready_o,
               axi_c_rvalid_o     => axi_c_rvalid_o,
               axi_c_rdata_o      => axi_c_rdata_o,
               axi_c_rresp_o      => axi_c_rresp_o,
               axi_c_rid_o        => axi_c_rid_o,
               axi_c_rlast_o      => axi_c_rlast_o,
               --
               --
               outport_awready_i  => axi_arb_awready_w,          -- xmem
               outport_wready_i   => axi_arb_wready_w,
               outport_bvalid_i   => axi_arb_bvalid_w,
               outport_bresp_i    => axi_arb_bresp_w,
               outport_bid_i      => axi_arb_bid_w,
               outport_arready_i  => axi_arb_arready_w,
               outport_rvalid_i   => axi_arb_rvalid_w,
               outport_rdata_i    => axi_arb_rdata_w,
               outport_rresp_i    => axi_arb_rresp_w,
               outport_rid_i      => axi_arb_rid_w,
               outport_rlast_i    => axi_arb_rlast_w,
               outport_awvalid_o  => axi_arb_awvalid_w,
               outport_awaddr_o   => axi_arb_awaddr_w,
               outport_awid_o     => axi_arb_awid_w,
               outport_awlen_o    => axi_arb_awlen_w,
               outport_awburst_o  => axi_arb_awburst_w,
               outport_wvalid_o   => axi_arb_wvalid_w,
               outport_wdata_o    => axi_arb_wdata_w,
               outport_wstrb_o    => axi_arb_wstrb_w,
               outport_wlast_o    => axi_arb_wlast_w,
               outport_bready_o   => axi_arb_bready_w,
               outport_arvalid_o  => axi_arb_arvalid_w,
               outport_araddr_o   => axi_arb_araddr_w,
               outport_arid_o     => axi_arb_arid_w,
               outport_arlen_o    => axi_arb_arlen_w,
               outport_arburst_o  => axi_arb_arburst_w,
               outport_rready_o   => axi_arb_rready_w );


  u_retime : axi4_retime
    generic map ( AXIDATA_W  => AXIDATA_W )                      -- select 32/64
    port map ( clk_i              => clk_i,
               xrst_i             => xrst_i,
               --
               inport_awvalid_i   => axi_arb_awvalid_w,
               inport_awaddr_i    => axi_arb_awaddr_w,
               inport_awid_i      => axi_arb_awid_w,
               inport_awlen_i     => axi_arb_awlen_w,
               inport_awburst_i   => axi_arb_awburst_w,
               inport_wvalid_i    => axi_arb_wvalid_w,
               inport_wdata_i     => axi_arb_wdata_w,
               inport_wstrb_i     => axi_arb_wstrb_w,
               inport_wlast_i     => axi_arb_wlast_w,
               inport_bready_i    => axi_arb_bready_w,
               inport_arvalid_i   => axi_arb_arvalid_w,
               inport_araddr_i    => axi_arb_araddr_w,
               inport_arid_i      => axi_arb_arid_w,
               inport_arlen_i     => axi_arb_arlen_w,
               inport_arburst_i   => axi_arb_arburst_w,
               inport_rready_i    => axi_arb_rready_w,
               inport_awready_o   => axi_arb_awready_w,
               inport_wready_o    => axi_arb_wready_w,
               inport_bvalid_o    => axi_arb_bvalid_w,
               inport_bresp_o     => axi_arb_bresp_w,
               inport_bid_o       => axi_arb_bid_w,
               inport_arready_o   => axi_arb_arready_w,
               inport_rvalid_o    => axi_arb_rvalid_w,
               inport_rdata_o     => axi_arb_rdata_w,
               inport_rresp_o     => axi_arb_rresp_w,
               inport_rid_o       => axi_arb_rid_w,
               inport_rlast_o     => axi_arb_rlast_w,
               --
               outport_awready_i  => xmem_awready_i,        -- from DDR
               outport_wready_i   => xmem_wready_i,         -- from DDR
               outport_bvalid_i   => xmem_bvalid_i,         -- from DDR
               outport_bresp_i    => xmem_bresp_i,          -- from DDR [1:0]
               outport_bid_i      => xmem_bid_i,            -- from DDR [3:0]
               outport_arready_i  => xmem_arready_i,        -- from DDR
               outport_rvalid_i   => xmem_rvalid_i,         -- from DDR
               outport_rdata_i    => xmem_rdata_i,          -- from DDR [31:0]
               outport_rresp_i    => xmem_rresp_i,          -- from DDR [1:0]
               outport_rid_i      => xmem_rid_i,            -- from DDR [3:0]
               outport_rlast_i    => xmem_rlast_i,          -- from DDR
               outport_awvalid_o  => xmem_awvalid_o,        -- to DDR
               outport_awaddr_o   => xmem_awaddr_o,         -- to DDR [31:0]
               outport_awid_o     => xmem_awid_o,           -- to DDR [3:0]
               outport_awlen_o    => xmem_awlen_o,          -- to DDR [7:0]
               outport_awburst_o  => xmem_awburst_o,        -- to DDR [1:0]
               outport_wvalid_o   => xmem_wvalid_o,         -- to DDR
               outport_wdata_o    => xmem_wdata_o,          -- to DDR [31:0]
               outport_wstrb_o    => xmem_wstrb_o,          -- to DDR [3:0]
               outport_wlast_o    => xmem_wlast_o,          -- to DDR
               outport_bready_o   => xmem_bready_o,         -- to DDR
               outport_arvalid_o  => xmem_arvalid_o,        -- to DDR
               outport_araddr_o   => xmem_araddr_o,         -- to DDR [31:0]
               outport_arid_o     => xmem_arid_o,           -- to DDR [3:0]
               outport_arlen_o    => xmem_arlen_o,          -- to DDR [7:0]
               outport_arburst_o  => xmem_arburst_o,        -- to DDR [1:0]
               outport_rready_o   => xmem_rready_o );       -- to DDR

end rtl;
