
Wed Apr 15 16:43:23 EEST 2026

Running quartus with riscv_tcm.qpf / riscv_tcm.qsf requires
  - 2-p ram ip block  (like in ../rtl/top_tcm/tcm_mem.vhd)
  - pll to generate 50MHz clock for soc (here 24.576MHz to 50MHz PLL)


  --  Arria 10 dual port ram, 64k
  component ram_2p
    port ( clock      : in  std_logic   := 'X';              -- clock
           data_a     : in  slv_31_00   := (others => 'X');  -- datain _a
           data_b     : in  slv_31_00   := (others => 'X');  -- datain_b
           address_a  : in  slv_15_00   := (others => 'X');  -- address_a
           address_b  : in  slv_15_00   := (others => 'X');  -- address_b
           wren_a     : in  std_logic   := 'X';              -- wren_a
           wren_b     : in  std_logic   := 'X';              -- wren_b
           byteena_b  : in  slv_03_00   := (others => 'X');  -- byte_enable_b
           q_a        : out slv_31_00;                       -- dataout_a
           q_b        : out slv_31_00 );                     -- dataout_b
  end component ram_2p;
