
#ifndef VSRV
#define VSRV

#define VSRV_IRQ_BASE          0x90000000
#define VSRV_TMR_BASE          0x91000000
#define VSRV_ULITE_BASE        0x92000000
#define VSRV_SPI_BASE          0x93000000
#define VSRV_GPIO_BASE         0x94000000
#define VSRV_UART2_BASE        0x95000000
#define VSRV_DMA_BASE          0x99000000
#define VSRV_IF_BASE           0x9B000000

#define  VSRV_TIMER_INT         0
#define  VSRV_ULITE_INT         1
#define  VSRV_SPI_INT           2
#define  VSRV_GP0_INT           3
#define  VSRV_UART2_INT         4
#define  VSRV_DMA_INT           5



// - - - - - IRQ CTRL - - - - -
#define IRQ_ISR          0x0000   // [RW]  Interrupt Status Register
#define IRQ_IPR          0x0004   // [R]   Interrupt Pending Register
#define IRQ_IER          0x0008   // [RW]  Interrupt Enable Register
#define IRQ_IAR          0x000C   // [W]   Interrupt Acknowledge Register
#define IRQ_SIE          0x0010   // [W]   Set Interrupt Enable bits
#define IRQ_CIE          0x0014   // [W]   Clear Interrupt Enable bits
#define IRQ_IVR          0x0018   // [RW]  Interrupt Vector Register
#define IRQ_MER          0x001C   // [RW]  Master Enable Register

// - - - - - TIMER - - - - -
#define TMR_CTRL0        0x0008   // [RW]  Control
#define TMR_CMP0         0x000C   // [RW]  Compare Value (interrupt on match)
#define TMR_VAL0         0x0010   // [RW]  Current Value
#define TMR_CTRL1        0x0014   // [RW]  Control
#define TMR_CMP1         0x0018   // [RW]  Compare value (interrupt on match)
#define TMR_VAL1         0x001C   // [RW]  Current value

// - - - - - UART LITE - - - - -
#define ULITE_RX         0x0000   // [R]   UART Data Register
#define ULITE_TX         0x0004   // [W]   UART Data Register
#define ULITE_ST         0x0008   // [R]   UART Status Register
#define ULITE_CTRL       0x000C   // [RW]  UART Configuration Register
#define ULITE_DIV        0x0010   // [RW]  UART Divider Register
//      ULITE_DIV[11:0]  = (CLK_FREQ/UART_SPEED)-1

#define    ULITE_ST_IE_B                    0x10     // 4  IRQ enabled
#define    ULITE_ST_TXFULL_B                0x08     // 3  TX fifo full
#define    ULITE_ST_TXEMPTY_B               0x04     // 2  TX fifo empty
#define    ULITE_ST_RXFULL_B                0x02     // 1  RX fifo full
#define    ULITE_ST_RXVALID_B               0x01     // 0  RX fifo valid

#define    ULITE_CTRL_IE_DEFAULT            0
#define    ULITE_CTRL_IE_B                  0x10     // 4  enable interrupt
#define    ULITE_CTRL_RST_RX_DEFAULT        0
#define    ULITE_CTRL_RST_RX_B              0x02     // 1  clear RX fifo
// #define ULITE_CTRL_RST_TX_DEFAULT        0
// #define ULITE_CTRL_RST_TX_B              0x01     // 0  clear TX fifo

#define ULITE_BAUD_RATE      1000000
#define ULITE_CLOCK_FREQ     50000000
#define ULITE_BASE_ADDR      0x92000000



// - - - - - SPI - - - - -
#define SPI_DGIER        0x001C   // [RW]  SPI Global Interrupt Enable Register
#define SPI_IPISR        0x0020   // [RW]  SPI Interrupt Status Register
#define SPI_IPIER        0x0028   // [RW]  SPI Interrupt Enable Register
#define SPI_SRR          0x0040   // [W]   SPI Software Reset Register
#define SPI_CR           0x0060   // [RW]  SPI Control Register
#define SPI_SR           0x0064   // [R]   SPI Status Register
#define SPI_DTR          0x0068   // [W]   SPI Data Transmit Register
#define SPI_DRR          0x006C   // [R]   SPI Data Receive Register
#define SPI_SSR          0x0070   // [RW]  SPI Slave Select Register

// - - - - - GPIO - - - - -
#define GPIO_DIR         0x0000   // [RW]  GPIO Configuration Register (1: out)
#define  GPIO_OENA       0x0000   // [RW]  GPIO Configuration Register (1: out)
#define GPIO_IN          0x0004   // [R]   GPIO Input Status
#define GPIO_OUT         0x0008   // [RW]  GPIO Output Control
#define GPIO_OUT_SET     0x000C   // [W]   GPIO Output Control Set
#define GPIO_OUT_CLR     0x0010   // [W]   GPIO Output Control Clr
#define GPIO_INT_MASK    0x0014   // [RW]  GPIO Interrupt Enable Mask
#define GPIO_INT_SET     0x0018   // [W]   GPIO Interrupt Set
#define GPIO_INT_CLR     0x001C   // [W]   GPIO Interrupt Clear
#define GPIO_INT_STATUS  0x0020   // [R]   GPIO Interrupt Raw Status
#define GPIO_INT_LEVEL   0x0024   // [RW]  GPIO Interrupt Level
#define GPIO_INT_MODE    0x0028   // [RW]  GPIO Interrupt Mode
#define GPIO_PD_ENA      0x002C   // PAD pull-down enable  ! DEFAULT ON  = HIGH
#define GPIO_PU_ENA      0x0030   // PAD pull-up enable    ! DEFAULT OFF = LOW



// - - - - - RISCV IF - - - - -
#define RVIF_PLL_ST      0x0000           // rv pll config bits [8:0]
#define RVIF_UART_CFG    0x0004           // sw config reg, NC



// - - - - - DMA MEM2MEM - - - - -
#define DMA_LEN          0x0000          // DMA set transfer LEN in words 0-0xFF
#define DMA_SRC_ADDR     0x0001          // DMA source address
#define DMA_DEST_ADDR    0x0002          // DMA destination address
#define DMA_CTRL         0x0003          // DMA control register
#define   DMA_CTRL_ENA            (1<<0) // DMA enable (start op)




// - - - - - UART2 16550 - - - - -
#define UART2_CLOCK_FREQ           50000000 
#define UART2_BAUD_RATE            1000000
#define NS16550A_UART2_CTRL_ADDR   0x95000000

enum {
    UART_RBR      = 0x00,  /* Receive Buffer Register */
    UART_THR      = 0x00,  /* Transmit Hold Register */
    UART_IER      = 0x01,  /* Interrupt Enable Register */
    UART_DLL      = 0x00,  /* Divisor LSB (LCR_DLAB) */
    UART_DLM      = 0x01,  /* Divisor MSB (LCR_DLAB) */
    UART_FCR      = 0x02,  /* FIFO Control Register */
    UART_LCR      = 0x03,  /* Line Control Register */
    UART_MCR      = 0x04,  /* Modem Control Register */
    UART_LSR      = 0x05,  /* Line Status Register */
    UART_MSR      = 0x06,  /* Modem Status Register */
    UART_SCR      = 0x07,  /* Scratch Register */

    UART_LCR_DLAB = 0x80,  /* Divisor Latch Bit */
    UART_LCR_8BIT = 0x03,  /* 8-bit */
    UART_LCR_PODD = 0x08,  /* Parity Odd */

    UART_LSR_DA   = 0x01,  /* Data Available */
    UART_LSR_OE   = 0x02,  /* Overrun Error */
    UART_LSR_PE   = 0x04,  /* Parity Error */
    UART_LSR_FE   = 0x08,  /* Framing Error */
    UART_LSR_BI   = 0x10,  /* Break indicator */
    UART_LSR_RE   = 0x20,  /* THR is empty */
    UART_LSR_RI   = 0x40,  /* THR is empty and line is idle */
    UART_LSR_EF   = 0x80,  /* Erroneous data in FIFO */
};


void ulite_init();
void uart2_init();
void printf(const char *fmt, ...);


#endif
