#!/bin/tcsh -f

  ###
  ### 
  ###

  ### USAGE:  ./compile_top_cache.sh
  ###         OR
  ###         source compile_top_cache.sh


  which vsim >& /dev/null
  if ( $status != 0 ) then
    printf "\n\n  ERROR: Modelsim not found\n\n"
    exit;
  endif


  if ( ! (-e  libraries/) ) then
    vlib           ./libraries/ ;
    vlib           ./libraries/work/ ;
    vmap  work     ./libraries/work/ ;
  endif

  set hdl_root   = ../rtl

  set opt   = "-93 -nologo -quiet -lint -check_synthesis"
  set opttb = "-93 -nologo -quiet -lint"


  # - - - - - - - - - - - - - - START RISCV CPU - - - - - - - - - - - - - -
  printf "                                                               \n"
  printf " COMPILING RISCV CPU:                                          \n"
  printf "   rv_pkg               (configuration/parameters file)        \n"
  printf "   rv_cpu                :  /u_cpu                             \n"
  printf "   |--rv_fetch           :  /u_core/u_fetch                    \n"
  printf "   |--rv_decode          :  /u_core/u_decode                   \n"
  printf "   |   |--rv_decoder     :  /u_core/u_decode/u_dec             \n"
  printf "   |--rv_issue           :  /u_core/u_issue                    \n"
  printf "   |   |--rv_pipe_ctrl   :  /u_core/u_issue/u_pipe_ctrl        \n"
  printf "   |   |--rv_regfile     :  /u_core/u_issue/u_regfile          \n"
  printf "   |--rv_exec            :  /u_core/u_exec                     \n"
  printf "   |   |--rv_alu         :  /u_core/u_exec/u_alu               \n"
  printf "   |   |--rv_multiplier  :  /u_core/u_exec/u_mul               \n"
  printf "   |   |--rv_divider     :  /u_core/u_exec/u_div               \n"
  printf "   |--rv_lsu             :  /u_core/u_lsu                      \n"
  printf "   |-- |-rv_lsu_fifo     :  /u_core/u_lsu/u_lsu_request        \n"
  printf "   |--rv_csr             :  /u_core/u_csr                      \n"
  printf "   |   |--rv_csr_rf      :  /u_core/u_csr/u_csr_rf             \n"
  printf "   |--rv_mmu             :  /u_core/u_mmu                      \n"
  printf "                                                               \n"

  vcom ${opt} -work work $hdl_root/core/rv_pkg.vhd

  vcom ${opt} -work work $hdl_root/core/rv_fetch.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_decoder.vhd
  vcom ${opt} -work work $hdl_root/core/rv_decode.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_multiplier.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_divider.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_alu.vhd
  vcom ${opt} -work work $hdl_root/core/rv_exec.vhd

  vcom ${opt} -work work    $hdl_root/core/rv_pipe_ctrl.vhd
  vcom ${opt} -work work    $hdl_root/core/rv_regfile.vhd
  vcom ${opt} -work work $hdl_root/core/rv_issue.vhd

  vcom ${opt} -work work    $hdl_root/core/rv_csr_rf.vhd
  vcom ${opt} -work work $hdl_root/core/rv_csr.vhd
  vcom ${opt} -work work $hdl_root/core/rv_lsu.vhd

  vcom ${opt} -work work $hdl_root/core/rv_mmu.vhd

  vcom ${opt} -work work $hdl_root/core/rv_cpu.vhd
  # - - - - - - - - - - - - - - END RISCV CPU - - - - - - - - - - - - - -



  # - - - - - - - - - - - - - START RISCV CORE - - - - - - - - - - - - -
  printf "                                                               \n"
  printf " COMPILING ICACHE:                                             \n"
  printf "   icache (2x8kB)         :  /u_icache          (2 x 2KW)      \n"
  printf "   |--tag_ram             :  /u_icache/u_tag0   (19x256)       \n"
  printf "   |--tag_ram             :  /u_icache/u_tag1   (19x256)       \n"
  printf "   |--data_ram            :  /u_icache/u_data0  (2KW)          \n"
  printf "   |--data_ram            :  /u_icache/u_data1  (2KW)          \n"
  printf "                                                               \n"

  vcom ${opttb} -work work  $hdl_root/top_cache/memories.vhd 
  vcom ${opttb} -work work  $hdl_root/top_cache/icachew.vhd


  printf "                                                               \n"
  printf " COMPILING DCACHE:                                             \n"
  printf "   dcache  (2x8kB)        : /u_dcache         (2 x 2KW)        \n"
  printf "   |  |--tag_ram          : /u_dcache/u_tag0  (20x256)         \n"
  printf "   |  |--tag_ram          : /u_dcache/u_tag1  (20x256)         \n"
  printf "   |  |--data_ram         : /u_dcache/u_data0 (2KW)            \n"
  printf "   |  |--data_ram         : /u_dcache/u_data1 (2KW)            \n"
  printf "                                                               \n"

  vcom ${opt}   -work work  $hdl_root/top_cache/dcachew.vhd

  printf "                                                               \n"
  printf " COMPILING RV_CORE:                                            \n"
  printf "   rv_core                : /u_core                            \n"
  printf "   rv_cpu                 : /u_core/u_cpu                      \n"
  printf "   icachew                : /u_core/u_icache                   \n"
  printf "   dcachew                : /u_core/u_dcache                   \n"
  printf "   axi_wrapper            : /u_core/u_axi                      \n"
  printf "   |--rom32x16k           : /u_core/u_axi/u_rvirom16k          \n"
  printf "   dma                    : /u_core/u_dma                      \n"
  printf "                                                               \n"

  # cpu + caches (external AXI IF)
  vcom ${opt}   -work work  $hdl_root/top_cache/axi_wrapper_rom.vhd
  vcom ${opt}   -work work  $hdl_root/soc/dma.vhd
  vcom ${opt}   -work work  $hdl_root/top_cache/rv_core.vhd
  # - - - - - - - - - - - - - END RISCV CORE - - - - - - - - - - - - -




  # - - - - - - - - - - - - - START RISCV SOC - - - - - - - - - - - - -
  printf "                                                                 \n"
  printf " COMPILING RISCV_SOC (vsperips, axi_if, dbg_bridge)              \n"

  vcom ${opt} -work work  $hdl_root/soc/vsgpio.vhd
  vcom ${opt} -work work  $hdl_root/soc/vsspi_lite.vhd
  vcom ${opt} -work work  $hdl_root/soc/vsuart_lite.vhd
  vcom ${opt} -work work  $hdl_root/soc/vstimer.vhd
  vcom ${opt} -work work  $hdl_root/soc/vsirq_ctrl.vhd
  vcom ${opt} -work work  $hdl_root/soc/rv_if.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_pkg.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_tfifo.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_rfifo.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_transmitter.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart_receiver.vhd
  vcom ${opt} -work work     $hdl_root/soc/uart16550/uart16550.vhd

  vcom ${opt} -work work  $hdl_root/soc/vsperips.vhd

  vcom ${opt} -work work  $hdl_root/top_cache/axi4_arb.vhd
  vcom ${opt} -work work  $hdl_root/top_cache/axi4_retime.vhd
  vcom ${opt} -work work  $hdl_root/top_cache/axi_mem_if.vhd

  vcom ${opt} -work work  $hdl_root/dbg/dbg_bridge_fifo.vhd
  vcom ${opt} -work work  $hdl_root/dbg/dbg_bridge_uart.vhd
  vcom ${opt} -work work  $hdl_root/dbg/dbg_bridge.vhd

  vcom ${opt} -work work  $hdl_root/soc/rv_soc.vhd
  # - - - - - - - - - - - - - END RISCV SOC - - - - - - - - - - - - -



  #
  # testbenches
  #
  ### TB FOR RV_SOC WITH AXI_SRAM (not DDR model)
  vcom ${opttb} -work work  $hdl_root/tb/axi_sram.vhd
  vcom ${opttb} -work work  $hdl_root/tb/rv_soc_tb.vhd


  unset hdl_root
  unset opt
  unset opttb

  printf '                                                                 \n'
  printf '  - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\n'
  printf '                                                                 \n'
  printf ' RV_SOC_TB (with axi_sram, no DDR) :                             \n'
  printf '  1) vsim -lib work rv_soc_tb -do "add wave rv_soc_tb/*;'
  printf '   add wave rv_soc_tb/u_rv_soc/* ;" &                            \n'
  printf ' OR                                                              \n'
  printf '  2) vsim -lib work rv_soc_tb -do wave_rv_soc.do &;              \n'
  printf '     restart -f ;                                                \n'
  printf '     force -freeze /rv_soc_tb/uart_txd_i 1 0 ;                   \n'
  printf '     run 1 us ;                                                  \n'
  printf '     force -freeze /rv_soc_tb/u_rv_soc/rv_core_ena_w 1 0 ;       \n'
  printf '     run 500 us ;                                                \n'
  printf '                                                                 \n'
  printf ' RV_SOC_TB WITH OTHER .MIF FILE :                                \n'
  printf '  3) vsim -lib work rv_soc_tb -G/rv_soc_tb/u_axi_sram/'
  printf 'mif_file_g="../rtl/tb/linux_riscv_soc.elf.mif" '
  printf '-do wave_rv_soc.do &; \n'
  printf '                                                                 \n'
  printf '  - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -\n'
