00001
00004 #ifndef __VS1000_H__
00005 #define __VS1000_H__
00006
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00016
00017 #include <vstypes.h>
00018
00019 #define IROM_START 0x4000
00020 #define IROM_SIZE 0x4a80
00021 #define XROM_START 0x4000
00022 #define XROM_SIZE 0x0c00
00023 #define YROM_START 0x4000
00024 #define YROM_SIZE 0x2800
00025
00026 #define XRAM_START 0x0
00027 #define XRAM_SIZE 0x3400
00028 #define YRAM_START 0x0
00029 #define YRAM_SIZE 0x4000
00030 #define IRAM_START 0x0
00031 #define IRAM_SIZE 0x800
00032
00033
00034
00035
00036
00037
00038 #define DCT_START 0x1000
00039 #define STACK_START 0x1800
00040 #define STACK_SIZE 0x200
00041 #define DEBUG_STACK (STACK_START+STACK_SIZE-32)
00042 #define OTHERS_START 0x0800
00043 #define YPREV0_START 0x0000
00044 #define YPREV1_START 0x0400
00045 #define AUDIO_START 0x0000
00046
00047 #define INTV_GPIO1 10
00048 #define INTV_GPIO0 9
00049 #define INTV_REGU 8
00050 #define INTV_TIM1 7
00051 #define INTV_TIM0 6
00052 #define INTV_RX 5
00053 #define INTV_TX 4
00054 #define INTV_NFLSH 3
00055 #define INTV_USB 2
00056 #define INTV_SPI 1
00057 #define INTV_DAC 0
00058
00059 #define INTF_GPIO1 (1<<INTV_GPIO1)
00060 #define INTF_GPIO0 (1<<INTV_GPIO0)
00061 #define INTF_REGU (1<<INTV_REGU)
00062 #define INTF_TIM1 (1<<INTV_TIM1)
00063 #define INTF_TIM0 (1<<INTV_TIM0)
00064 #define INTF_RX (1<<INTV_RX)
00065 #define INTF_TX (1<<INTV_TX)
00066 #define INTF_NFLSH (1<<INTV_NFLSH)
00067 #define INTF_USB (1<<INTV_USB)
00068 #define INTF_SPI (1<<INTV_SPI)
00069 #define INTF_DAC (1<<INTV_DAC)
00070
00071 #define INT_EN_NONE 0
00072 #define INT_EN_GPIO1 INTV_GPIO1
00073 #define INT_EN_GPIO0 INTV_GPIO0
00074 #define INT_EN_REGU INTV_REGU
00075 #define INT_EN_TIM1 INTV_TIM1
00076 #define INT_EN_TIM0 INTV_TIM0
00077 #define INT_EN_RX INTV_RX
00078 #define INT_EN_TX INTV_TX
00079 #define INT_EN_NFLSH INTV_NFLSH
00080 #define INT_EN_USB INTV_USB
00081 #define INT_EN_SPI INTV_SPI
00082 #define INT_EN_DAC INTV_DAC
00083
00084
00085
00086 #define SCI_SYSTEM 0xC000
00087 #define SCISYSF_CLKDIV 0x8000
00088 #define SCISYSF_AVDD (1<<10)
00089 #define SCISYSF_IOVDD (1<<5)
00090 #define SCISYSF_CVDD (1<<0)
00091 #define SCI_STATUS 0xC001
00092
00093 #define SCISTF_SLOW_CLKMODE (1<<15)
00094 #define SCISTF_USB_DN_OUT (1<<14)
00095 #define SCISTF_USB_DP_OUT (1<<13)
00096 #define SCISTF_USB_DDR (1<<12)
00097
00098 #define SCISTF_VCM_OVERLOAD (1<<11)
00099 #define SCISTF_VCM_DISABLE (1<<10)
00100
00101 #define SCISTF_USB_DP (1<<9)
00102 #define SCISTF_USB_DN (1<<8)
00103 #define SCISTF_USB_DIFF_ENA (1<<7)
00104 #define SCISTF_USB_PULLUP_ENA (1<<6)
00105 #define SCISTF_REGU_POWERLOW (1<<5)
00106 #define SCISTF_REGU_POWERBUT (1<<4)
00107 #define SCISTF_ANADRV_PDOWN (1<<3)
00108 #define SCISTF_ANA_PDOWN (1<<2)
00109 #define SCISTF_REGU_CLOCK (1<<1)
00110 #define SCISTF_REGU_SHUTDOWN (1<<0)
00111
00112 #define SCI_DEBUG 0xC002
00113
00114 #define GPIO0_MODE 0xC010
00115 #define GPIO1_MODE 0xC011
00116
00117 #define DAC_VOL 0xC012
00118
00119 #define FREQCTLL 0xC013
00120 #define FREQCTLH 0xC014
00121
00122 #define FCH_MUL0_B 4
00123 #define FCH_MUL1_B 5
00124 #define FCH_MUL2_B 6
00125 #define FCH_MUL3_B 7
00126 #define FCH_DIV_INCLK_B 8
00127 #define FCH_FORCE_PLL_B 9
00128
00129 #define FCH_VCO_OUT_ENA_B 11
00130 #define FCH_PLL_SET_LOCK_B 12
00131 #define FCH_PLL_LOCKED_B 13
00132
00133 #define FCH_MUL0 (1<<FCH_MUL0_B)
00134 #define FCH_MUL1 (1<<FCH_MUL1_B)
00135 #define FCH_MUL2 (1<<FCH_MUL2_B)
00136 #define FCH_MUL3 (1<<FCH_MUL3_B)
00137 #define FCH_DIV_INCLK (1<<FCH_DIV_INCLK_B)
00138 #define FCH_FORCE_PLL (1<<FCH_FORCE_PLL_B)
00139
00140 #define FCH_VCO_OUT_ENA (1<<FCH_VCO_OUT_ENA_B)
00141 #define FCH_PLL_SET_LOCK (1<<FCH_PLL_SET_LOCK_B)
00142 #define FCH_PLL_LOCKED (1<<FCH_PLL_LOCKED_B)
00143
00144
00145 #define DAC_LEFT 0xC015
00146 #define DAC_RIGHT 0xC016
00147
00148 #define WDOG_CONFIG 0xC020
00149 #define WDOG_RESET 0xC021
00150 #define WDOG_DUMMY 0xC022
00151 #define WDOG_RESET_VAL 0x4ea9
00152
00153 #define UART_STATUS 0xC028
00154 #define UART_DATA 0xC029
00155 #define UART_DATAH 0xC02A
00156 #define UART_DIV 0xC02B
00157
00158 #define UART_ST_RXORUN (1<<3)
00159 #define UART_ST_RXFULL (1<<2)
00160 #define UART_ST_TXFULL (1<<1)
00161 #define UART_ST_TXRUNNING (1<<0)
00162
00163
00164 #define TIMER_CONFIG 0xC030
00165 #define TIMER_ENABLE 0xC031
00166 #define TIMER_T0L 0xC034
00167 #define TIMER_T0H 0xC035
00168 #define TIMER_T0CNTL 0xC036
00169 #define TIMER_T0CNTH 0xC037
00170 #define TIMER_T1L 0xC038
00171 #define TIMER_T1H 0xC039
00172 #define TIMER_T1CNTL 0xC03A
00173 #define TIMER_T1CNTH 0xC03B
00174
00175 #define GPIO0_DDR 0xC040
00176 #define GPIO0_ODATA 0xC041
00177 #define GPIO0_IDATA 0xC042
00178 #define GPIO0_INT_FALL 0xC043
00179 #define GPIO0_INT_RISE 0xC044
00180 #define GPIO0_INT_PEND 0xC045
00181 #define GPIO0_SET_MASK 0xC046
00182 #define GPIO0_CLEAR_MASK 0xC047
00183 #define GPIO0_BIT_CONF 0xC048
00184 #define GPIO0_BIT_ENG0 0xC049
00185 #define GPIO0_BIT_ENG1 0xC04A
00186
00187 #define GPIO0_READY 0x0100
00188 #define GPIO0_RD 0x0200
00189 #define GPIO0_CS1 0x0400
00190 #define GPIO0_WR 0x0800
00191 #define GPIO0_CLE 0x1000
00192 #define GPIO0_ALE 0x2000
00193
00194 #define GPIO1_DDR 0xC050
00195 #define GPIO1_ODATA 0xC051
00196 #define GPIO1_IDATA 0xC052
00197 #define GPIO1_INT_FALL 0xC053
00198 #define GPIO1_INT_RISE 0xC054
00199 #define GPIO1_INT_PEND 0xC055
00200 #define GPIO1_SET_MASK 0xC056
00201 #define GPIO1_CLEAR_MASK 0xC057
00202 #define GPIO1_BIT_CONF 0xC058
00203 #define GPIO1_BIT_ENG0 0xC059
00204 #define GPIO1_BIT_ENG1 0xC05A
00205
00206 #define SPI0_CONFIG 0xC068
00207 #define SPI0_CLKCONFIG 0xC069
00208 #define SPI0_STATUS 0xC06A
00209 #define SPI0_DATA 0xC06B
00210 #define SPI0_FSYNC 0xC06C
00211
00212 #define SPI_CF_INTXCS (0<<6)
00213 #define SPI_CF_FALLXCS (2<<6)
00214 #define SPI_CF_RISEXCS (3<<6)
00215 #define SPI_CF_MASTER (1<<5)
00216 #define SPI_CF_SLAVE (0<<5)
00217 #define SPI_CF_DLEN (1<<1)
00218 #define SPI_CF_DLEN8 (7<<1)
00219 #define SPI_CF_DLEN16 (15<<1)
00220 #define SPI_CF_FSIDLE1 (1<<0)
00221 #define SPI_CF_FSIDLE0 (0<<0)
00222
00223
00224
00225
00226
00227
00228 #define SPI_CC_CLKDIV (1<<2)
00229
00230 #define SPI_ST_BREAK (1<<5)
00231 #define SPI_ST_RXORUN (1<<4)
00232 #define SPI_ST_RXFULL (1<<3)
00233 #define SPI_ST_TXFULL (1<<2)
00234 #define SPI_ST_TXRUNNING (1<<1)
00235 #define SPI_ST_TXURUN (1<<0)
00236
00237
00238 #define NFLSH_CTRL 0xC060
00239 #define NFLSH_CF_LCD_CE_MODE (1<<8)
00240 #define NFLSH_CF_INT_ENABLE (1<<7)
00241 #define NFLSH_CF_NF_RESET (1<<6)
00242 #define NFLSH_CF_WAITSTATES (1<<0)
00243 #define NFLSH_LPL 0xC061
00244 #define NFLSH_CP_LPH 0xC062
00245 #define NFLSH_DATA 0xC063
00246 #define NFLSH_NFIF 0xC064
00247 #define NFLSH_NB_BYTECNT (8)
00248 #define NFLSH_NF_BYTECNT (1<<NFLSH_NB_BYTECNT)
00249 #define NFLSH_NF_USE_DBUF (1<<7)
00250 #define NFLSH_NF_POINTER (1<<2)
00251 #define NFLSH_NF_START (1<<1)
00252 #define NFLSH_NF_READ (1<<0)
00253 #define NFLSH_DSPIF 0xC065
00254 #define NFLSH_DB_POINTER (4)
00255 #define NFLSH_DF_POINTER (1<<NFLSH_DB_POINTER)
00256 #define NFLSH_DF_ENA_DBUF (1<<3)
00257 #define NFLSH_DF_READ (1<<2)
00258 #define NFLSH_DF_ECC_CALC (1<<1)
00259 #define NFLSH_DF_ECC_RESET (1<<0)
00260 #define NFLSH_ECC_CNT 0xC066
00261
00262
00263 #define INT_ENABLE 0xC070
00264 #define INT_ENABLEL 0xC070
00265 #define INT_ENABLEH 0xC072
00266 #define INT_ORIGIN 0xC074
00267 #define INT_VECTOR 0xC076
00268 #define INT_ENCOUNT 0xC077
00269 #define INT_GLOB_DIS 0xC078
00270 #define INT_GLOB_EN 0xC079
00271
00272
00273
00274
00275 #define USB_BASE 0xC080U
00276
00277
00278
00279 #define USB_RECV_MEM 0x2C00
00280 #define USB_SEND_MEM 0x3000
00281 #define PERIP_IN_X
00282
00283 #ifdef PERIP_IN_X
00284 #define PERIP(x) USEX(x)
00285 #else
00286 #define PERIP(x) USEY(x)
00287 #endif
00288
00289 #ifdef ASM
00290
00291 #ifdef PERIP_IN_X
00292 #define STP stx
00293 #define LDP ldx
00294 #else
00295 #define STP sty
00296 #define LDP ldy
00297 #endif
00298 #define MR_FRACT 0x000
00299
00300 #else
00301
00302
00303
00304
00305
00306
00307
00308 void SpiBoot(register __a0 short clkConf, register __i2 short addr,
00309 register __i0 short m24);
00310
00311 void SpiLoad(register __i2 short startAddr, register __i0 short m24);
00312 void SpiDelay(register __a0 u_int16 wait);
00313 auto u_int16 SpiSendReceive(register __a0 u_int16 data);
00314
00315 void Restart(void);
00316
00317
00320 void IdleHook(void);
00325 auto u_int16 InitFileSystem(void);
00331 auto s_int16 OpenFile(register __c0 u_int16 fileNum);
00340 auto s_int16 ReadFile(register __i3 u_int16 *buf,
00341 register __c1 s_int16 byteOff,
00342 register __c0 s_int16 byteSize
00343 );
00349 u_int32 Seek(register __reg_a u_int32 pos);
00354 u_int32 Tell(void);
00360 auto u_int16 ReadDiskSector(register __i0 u_int16 *buffer,
00361 register __a u_int32 sector);
00362
00368 auto u_int16 MapperReadDiskSector(register __i0 u_int16 *buffer,
00369 register __a u_int32 sector);
00370
00376 void Disable(void);
00379 void Enable(void);
00382 void Sleep(void);
00385 void NullHook(void);
00391 void *SetHookFunction(register __i0 u_int16 hook, register __a0 void *newFunc);
00392
00395 void BootFromX(register __i0 u_int16 *start);
00396
00397 void SinTest(void);
00398 void MemTests(register short __b0 muxTestResult);
00399
00401 enum voltIdx {
00402
00403 voltCorePlayer = 0,
00404 voltIoPlayer,
00405 voltAnaPlayer,
00406 voltCoreUSB,
00407 voltIoUSB,
00408 voltAnaUSB,
00409 voltCoreSuspend,
00410 voltIoSuspend,
00411 voltAnaSuspend,
00412 voltCoreUser,
00413 voltIoUser,
00414 voltAnaUser,
00415 voltEnd
00416 };
00417 extern u_int16 voltages[voltEnd];
00419 void BusyWait10(void);
00421 void PowerSetVoltages(u_int16 volt[3]);
00424 void PowerOff(void);
00430 void RealPowerOff(void);
00433 u_int16 PlayCurrentFile(void);
00443 u_int16 RealPlayCurrentFile(void);
00446 void LoadCheck(struct CodecServices *cs, s_int16 n);
00456 void RealLoadCheck(struct CodecServices *cs, s_int16 n);
00459 u_int16 UnsupportedFile(struct CodecServices *cs);
00462 u_int16 DefUnsupportedFile(struct CodecServices *cs);
00463
00464 extern u_int16 g_dctlo[2048];
00465 extern __y u_int16 g_dcthi[2048];
00466 extern s_int16 g_others[2048];
00467 extern s_int16 g_yprev0[1024];
00468 extern s_int16 g_yprev1[1024];
00469
00475 struct FsMapper *FsMapRamCreate(struct FsPhysical *physical,
00476 u_int16 cacheSize);
00477
00478 void putch(register __a0 s_int16 ch);
00479 s_int16 getch(void);
00480 #endif
00481
00482
00483 #endif