#ifndef FPGA_I2S_H
#define FPGA_I2S_H

#define INTV_I2S         21
#define INTF1_I2S        (1 << (INTV_I2S - 16))

#define I2S_CF           0xFE60
#define I2S_CF_REG_BITS  14
#define I2S_LEFT_LSB     0xFE61
#define I2S_LEFT         0xFE62
#define I2S_RIGHT_LSB    0xFE63
#define I2S_RIGHT        0xFE64

#define I2S_CF_32B_B     13
#define I2S_CF_INTENA_B  12
#define I2S_CF_RXRFULL_B 11
#define I2S_CF_RXLFULL_B 10
#define I2S_CF_RXORUN_B   9
#define I2S_CF_TXRFULL_B  8
#define I2S_CF_TXLFULL_B  7
#define I2S_CF_TXURUN_B   6
#define I2S_CF_MODE_B     5
#define I2S_CF_FS_B       3
#define I2S_CF_ENA_B      2
#define I2S_CF_ENAMCK_B   1
#define I2S_CF_MASTER_B   0

#define I2S_CF_16B       (0 << I2S_CF_32B_B)
#define I2S_CF_32B       (1 << I2S_CF_32B_B)
#define I2S_CF_INTENA    (1 << I2S_CF_INTENA_B)
#define I2S_CF_RXRFULL   (1 << I2S_CF_RXRFULL_B)
#define I2S_CF_RXLFULL   (1 << I2S_CF_RXLFULL_B)
#define I2S_CF_RXORUN    (1 << I2S_CF_RXORUN_B)
#define I2S_CF_TXRFULL   (1 << I2S_CF_TXRFULL_B)
#define I2S_CF_TXLFULL   (1 << I2S_CF_TXLFULL_B)
#define I2S_CF_TXURUN    (1 << I2S_CF_TXURUN_B)
#define I2S_CF_MODE      (1 << I2S_CF_MODE_B)
#define I2S_CF_FS192K    (2 << I2S_CF_FS_B) /* 192kHz in 16-bit mode, 96kHz in 32-bit mode */
#define I2S_CF_FS96K     (1 << I2S_CF_FS_B) /* 96kHz in 16-bit mode, 48kHz in 32-bit mode */
#define I2S_CF_FS48K     (0 << I2S_CF_FS_B) /* 48kHz in 16-bit mode, 24kHz in 32-bit mode */
#define I2S_CF_FS        (1 << I2S_CF_FS_B)
#define I2S_CF_ENA       (1 << I2S_CF_ENA_B)
#define I2S_CF_ENAMCK    (1 << I2S_CF_ENA_B)
#define I2S_CF_MASTER    (1 << I2S_CF_MASTER_B)
#define I2S_CF_FS192K16B (I2S_CF_16B|I2S_CF_FS192K)
#define I2S_CF_FS96K16B  (I2S_CF_16B|I2S_CF_FS96K )
#define I2S_CF_FS48K16B  (I2S_CF_16B|I2S_CF_FS48K )
#define I2S_CF_FS96K32B  (I2S_CF_32B|I2S_CF_FS192K)
#define I2S_CF_FS48K32B  (I2S_CF_32B|I2S_CF_FS96K )
#define I2S_CF_FS24K32B  (I2S_CF_32B|I2S_CF_FS48K )

#endif
