#ifndef __VSRV_H__
#define __VSRV_H__

#define __VS1005H_H__


/*
  VSRV definition file. (C) 2023-2024 VLSI Solution.
  Version: HH & others 2024-04-16

  2024-04-16 Minor formatting fixes to make PReg generator work better.
  2024-04-15 Finalized first VS1005-independent version.
  2024-04-09 Replaced CLK_CF_MULT0 with CLK_CF_MULT and
             VSRV1_CLK_CF_MULT0 with VSRV1_CLK_CF_MULT.
  2023-12-21 Founded.
*/

#include <vstypes.h>

#define obsoleted(a) OBSOLETE##a

#define ROM_ID_VS1005G  0xbbd7e455U
#define ROM_ID_VS1005H0 0xb6f679e5U
#define ROM_ID_VS1005H  0x9af8c349U

#define ROM_EXEC_START 0x8000 //0x8000 // TODO: change to 0x8000 for ROM version

#define IROM_START 0x8000
#define IROM_SIZE  0x4000
/*#define XROM_START 0x8000
#define XROM_SIZE  0x8000
#define YROM_START 0x8000
#define YROM_SIZE  0x7c00*/

#define XRAM_START     0x0
#define XRAM_SIZE   0xffff
#define YRAM_START     0x0
#define YRAM_SIZE   0xffff
#define IRAM_START     0x0
#define IRAM_SIZE   0xffff

#define STACK_START   0x30
#define STACK_SIZE   0x3d0
#define DEBUG_STACK (STACK_START+STACK_SIZE-48)  /* 78..98.. need 18 + tmp */

#define ETHRAM_START   0x6400
#define ETHRAM_SIZE     0x400
#define USBMEM_START   0xf400
#define USBMEM_SIZE     0x800
#define USB_RECV_START 0xf400
#define USB_SEND_START 0xf800

  // 
  // VSRV (2024-04-15):
  // 
  // Fast peripherals from 0xFC00 to 0xFDFF
  //    INT_ADDR_c     : FC00-FC1F
  //    CONTROL_ADDR_c : FC20-FC3F
  //    SPI0_ADDR_c    : FC40-FC4F
  //    SD_ADDR_c      : FC60-FC7F
  //    USB_ADDR_c     : FC80-FC9F
  //    GPIO0_ADDR_c   : FCA0-FCBF	// 14-bit GPIO port 0
  //    UART0_ADDR_c   : FCC0-FCC7
  //    UARTRV_ADDR_c  : FCC8-FCCF
  //    UARTMUX_ADDR_c : FCD0-FCDF
  //    SDRAM_ADDR_c   : FCE0-FD1F
  //    MASTER_CLOCK_c : FD20-FD3F

  // Slow peripherals from 0xFE00 to 0xFFFF
  //    WDOG_ADDR_c  : FE20-FE3F
  //    ADC_ADDR_c   : FE40-FE5F
  //    TIM_ADDR_c   : FE80-FE9F
  //    DAC_ADDR_c   : FEC0-FEDF


#define INTV_MCLKCNT    20
#define INTV_ETH        19
#define INTV_UARTMUX_RX 18
#define INTV_UARTMUX_TX 17
#define INTV_TIMER2     16

#define INTV_TIMER1     15
#define INTV_TIMER0     14
#define INTV_UART0_RX   13
#define INTV_UART0_TX   12
#define INTV_UARTRV_RX  11
#define INTV_UARTRV_TX  10 //mono AD
#define INTV_SDM         9
#define INTV_SRC         8
#define INTV_GPIO0       7
#define INTV_MAC0        6  //stereo AD
#define INTV_MAC1        5  //FM decimator
#define INTV_BUSERR      4
#define INTV_SPI0        3
#define INTV_SD          2
#define INTV_USB         1
#define INTV_DAC         0


#define INTF1_MCLKCNT    (1<<(INTV_MCLKCNT-16))
#define INTF1_ETH        (1<<(INTV_ETH-16))
#define INTF1_UARTMUX_RX (1<<(INTV_UARTMUX_RX-16))
#define INTF1_UARTMUX_TX (1<<(INTV_UARTMUX_TX-16))
#define INTF1_TIMER2     (1<<(INTV_TIMER2-16))

#define INTF_TIMER1    (1<<INTV_TIMER1)
#define INTF_TIMER0    (1<<INTV_TIMER0)
#define INTF_UART0_RX  (1<<INTV_UART0_RX)
#define INTF_UART0_TX  (1<<INTV_UART0_TX)
#define INTF_UARTRV_RX (1<<INTV_UARTRV_TX)
#define INTF_UARTRV_TX (1<<INTV_UARTRV_TX)
#define INTF_SDM       (1<<INTV_SDM)
#define INTF_SRC       (1<<INTV_SRC)
#define INTF_GPIO0     (1<<INTV_GPIO0)
#define INTF_MAC0      (1<<INTV_MAC0)
#define INTF_MAC1      (1<<INTV_MAC1)
#define INTF_BUSERR    (1<<INTV_BUSERR)
#define INTF_SPI0      (1<<INTV_SPI0)
#define INTF_SD        (1<<INTV_SD)
#define INTF_USB       (1<<INTV_USB)
#define INTF_DAC       (1<<INTV_DAC)

#define INT_ENABLE0_LP 	0xFC00	/**< Sources  0..15, low priority bits  */
#define INT_ENABLE1_LP 	0xFC01	/**< Sources 16..31, low priority bits  */
#define INT_ENABLE0_HP 	0xFC02	/**< Sources  0..15, high priority bits */
#define INT_ENABLE1_HP 	0xFC03	/**< Sources 16..31, high priority bits */
#define INT_ORIGIN0  	0xFC04
#define INT_ORIGIN1  	0xFC05
#define INT_VECTOR  	0xFC06
#define INT_ENCOUNT 	0xFC07
#define INT_GLOB_DIS 	0xFC08
#define INT_GLOB_ENA	0xFC09




/* Peripheral I/O control */

/* This used to be called GPIO0_MODE */
#define GPIO0_PERIPMODE       0xFC30
#define GPIO0_PERIPMODE_REG_BITS 12

/* GPIO definitions */


#define GPIO0_UART_TX_B    ( 2)
#define GPIO0_UART_RX_B    ( 3)
#define GPIO0_SPI0_SCLK_B  ( 4)
#define GPIO0_SPI0_XCS_B   ( 5)
#define GPIO0_SPI0_MISO_B  ( 6)
#define GPIO0_SPI0_MOSI_B  ( 7)
#define GPIO0_SD_CLK_B     ( 8)
#define GPIO0_SD_CMD_B     ( 9)
#define GPIO0_SD_D0_B      (10)
#define GPIO0_SD_D1_B      (11)
#define GPIO0_SD_D2_B      (12)
#define GPIO0_SD_D3_B      (13)

#define GPIO0_UART_TX    (1<< 2)
#define GPIO0_UART_RX    (1<< 3)
#define GPIO0_SPI0_SCLK  (1<< 4)
#define GPIO0_SPI0_XCS   (1<< 5)
#define GPIO0_SPI0_MISO  (1<< 6)
#define GPIO0_SPI0_MOSI  (1<< 7)
#define GPIO0_SD_CLK     (1<< 8)
#define GPIO0_SD_CMD     (1<< 9)
#define GPIO0_SD_D0      (1<<10)
#define GPIO0_SD_D1      (1<<11)
#define GPIO0_SD_D2      (1<<12)
#define GPIO0_SD_D3      (1<<13)





#define GPIO_MAP_BASE 0xFC20
#define GPIO_MAP1_0   0xFC20
#define GPIO_MAP3_2   0xFC21
#define GPIO_MAP5_4   0xFC22
#define GPIO_MAP7_6   0xFC23
#define GPIO_MAP9_8   0xFC24
#define GPIO_MAP11_10 0xFC25
#define GPIO_MAP13_12 0xFC26
#define GPIO_MAP_CLR  0xFC27


#define GMAP_NONE           0x0
#define GMAP_SPI_XCS        0x1
#define GMAP_SPI_SCLK       0x2
#define GMAP_SPI_MISO       0x3
#define GMAP_SPI_MOSI       0x4
#define GMAP_UART_RX        0x5
#define GMAP_UART_TX        0x6
#define GMAP_SD_CLK         0x7
#define GMAP_SD_CMD         0x8
#define GMAP_SD_D0          0x9
#define GMAP_SD_D1          0xa
#define GMAP_SD_D2          0xb
#define GMAP_SD_D3          0xc
#define GMAP_MEMS_CLK       0xd
#define GMAP_MEMS_DI        0xe
#define GMAP_USB_VCOOUT     0xf
#define GMAP_VSRV1_GPIO    0x10
#define GMAP_VSRV1_SPIXCS  0x11
#define GMAP_VSRV1_SPISCLK 0x12
#define GMAP_VSRV1_SPIMISO 0x13
#define GMAP_VSRV1_SPIMOSI 0x14
#define GMAP_VSRV1_UARTRX0 0x15
#define GMAP_VSRV1_UARTTX0 0x16
#define GMAP_VSRV1_UARTRX1 0x17
#define GMAP_VSRV1_UARTTX1 0x18





/* VSDSP PLL clock control */
#define CLK_CF           0xFC33
#define CLK_CF_REG_BITS 14

#define CLK_CF_USBOFF_B         13
#define CLK_CF_UNUSED2_B        12
#define CLK_CF_LCKST_B          11
#define CLK_CF_DIV256_B         10
#define CLK_CF_DIV2_B            9
#define CLK_CF_LCKCHK_B          8
#define CLK_CF_UNUSED1_B         7
#define CLK_CF_USBCLK_B          6
#define CLK_CF_FORCEPLL_B        5
#define CLK_CF_DIVI_B            4
#define CLK_CF_MULT_B            0

#define CLK_CF_USBOFF    (1<<CLK_CF_USBOFF_B)
#define CLK_CF_UNUSED2   (1<<CLK_CF_RTCSLP_B)
#define CLK_CF_LCKST     (1<<CLK_CF_LCKST_B)
#define CLK_CF_DIV256    (1<<CLK_CF_DIV256_B)
#define CLK_CF_DIV2      (1<<CLK_CF_DIV2_B)
#define CLK_CF_LCKCHK    (1<<CLK_CF_LCKCHK_B)
#define CLK_CF_UNUSED1   (1<<CLK_CF_VCOOUT_B)
#define CLK_CF_USBCLK    (1<<CLK_CF_USBCLK_B)
#define CLK_CF_FORCEPLL  (1<<CLK_CF_FORCEPLL_B)
#define CLK_CF_DIVI      (1<<CLK_CF_DIVI_B)
#define CLK_CF_MULT      (1<<CLK_CF_MULT_B)

#define CLK_CF_MULT_MASK (15*CLK_CF_MULT)



#define UVCO_TST           0xFC3F
#define UVCO_TST_REG_BITS 8

#define UVCO_TST_SEL_B          4
#define UVCO_TST_ODIV_B         0

#define UVCO_TST_SEL      (1<<4)
#define UVCO_TST_ODIV     (1<<0)



/* RISC-V PLL clock control */

#define VSRV1_CLK_CF           0xFC2E
#define VSRV1_CLK_CF_REG_BITS 12

#define VSRV1_CLK_CF_LCKST_B         11
#define VSRV1_CLK_CF_DIV256_B        10
#define VSRV1_CLK_CF_DIV2_B           9
#define VSRV1_CLK_CF_LCKCHK_B         8
#define VSRV1_CLK_CF_FORCEPLL_B       5
#define VSRV1_CLK_CF_DIVI_B           4
#define VSRV1_CLK_CF_MULT_B           0

#define VSRV1_CLK_CF_LCKST     (1<<VSRV1_CLK_CF_LCKST_B)
#define VSRV1_CLK_CF_DIV256    (1<<VSRV1_CLK_CF_GDIV256_B)
#define VSRV1_CLK_CF_DIV2      (1<<VSRV1_CLK_CF_GDIV2_B)
#define VSRV1_CLK_CF_LCKCHK    (1<<VSRV1_CLK_CF_LCKCHK_B)
#define VSRV1_CLK_CF_FORCEPLL  (1<<VSRV1_CLK_CF_FORCEPLL_B)
#define VSRV1_CLK_CF_DIVI      (1<<VSRV1_CLK_CF_DIVI_B)
#define VSRV1_CLK_CF_MULT      (1<<VSRV1_CLK_CF_MULT_B)

#define VSRV1_CLK_CF_MULT_MASK (15*VSRV1_CLK_CF_MULT)



#define VSRV1_CF               0xFC2F

#define VSRV1_CF_RAMD_B       14
#define VSRV1_CF_ETHOVRRUN_B  12
#define VSRV1_CF_ETHMEMTST_B  10
#define VSRV1_CF_ETHRDENA_B    9
#define VSRV1_CF_ETHRDST_B     8
#define VSRV1_CF_SDRAM_B       4
#define VSRV1_CF_MUX_B         2
#define VSRV1_CF_INT_B         1
#define VSRV1_CF_ENABLE_B      0

#define VSRV1_CF_RAMD      (1<<VSRV1_CF_RAMD_B)
#define VSRV1_CF_ETHOVRRUN (1<<VSRV1_CF_ETHOVRRUN_B)
#define VSRV1_CF_ETHMEMTST (1<<VSRV1_CF_ETHMEMTST_B)
#define VSRV1_CF_ETHRDENA  (1<<VSRV1_CF_ETHRDENA_B)
#define VSRV1_CF_ETHRDST   (1<<VSRV1_CF_ETHRDST_B)
#define VSRV1_CF_SDRAM     (1<<VSRV1_CF_SDRAM_B)
#define VSRV1_CF_MUX       (1<<VSRV1_CF_MUX_B)
#define VSRV1_CF_INT       (1<<VSRV1_CF_INT_B)
#define VSRV1_CF_ENABLE    (1<<VSRV1_CF_ENABLE_B)


/* System setup registers */

#define CF_SYSTEM1 0xFC2B

#define CF_SYSTEM1_BUSERRI_B		15
#define CF_SYSTEM1_BUSERRST_UNUSED3_B	14
#define CF_SYSTEM1_DRIVE_B		12
#define CF_SYSTEM1_SD3_B		 9
#define CF_SYSTEM1_BUSERRST_UNUSED2_B	 6
#define CF_SYSTEM1_BUSERRST_B		 5
#define CF_SYSTEM1_BUSERRST_UNUSED1_B	 3
#define CF_SYSTEM1_YUSB_SEL_B		 2
#define CF_SYSTEM1_YETH_SEL_B		 1
#define CF_SYSTEM1_IROM_DES_B		 0

#define CF_SYSTEM1_BUSERRI		(1<<15)
#define CF_SYSTEM1_BUSERRST_UNUSED3	(1<<14)
#define CF_SYSTEM1_DRIVE		(1<<12)
#define CF_SYSTEM1_SD3			(1<< 9)
#define CF_SYSTEM1_BUSERRST_UNUSED2	(1<< 6)
#define CF_SYSTEM1_BUSERRST		(1<< 5)
#define CF_SYSTEM1_BUSERRST_UNUSED1	(1<< 3)
#define CF_SYSTEM1_YUSB_SEL		(1<< 2)
#define CF_SYSTEM1_YETH_SEL		(1<< 1)
#define CF_SYSTEM1_IROM_DES		(1<< 0)

#define CF_SYSTEM1_BUSERRI_MASK		(1<<CF_SYSTEM1_BUSERRI_B)
#define CF_SYSTEM1_DRIVE_MASK		(3<<CF_SYSTEM1_DRIVE_B)
#define CF_SYSTEM1_SD3_MASK		(7<<CF_SYSTEM1_SD3_B)


#define CF_SYSTEM2 0xFC2C
#define CF_SYSTEM2_REG_BITS 12

#define CF_SYSTEM2_FRAMPD_B	11
#define CF_SYSTEM2_ERAMPD_B	10
#define CF_SYSTEM2_URAMPD_B	 9
#define CF_SYSTEM2_YRAMPD_B	 8
#define CF_SYSTEM2_XRAMPD_B	 7
#define CF_SYSTEM2_UNUSED_B	 5
#define CF_SYSTEM2_XTALOFF_B	 4
#define CF_SYSTEM2_ROMD_B	 2
#define CF_SYSTEM2_RAMD_B	 0

#define CF_SYSTEM2_FRAMPD	(1<<11)
#define CF_SYSTEM2_ERAMPD	(1<<10)
#define CF_SYSTEM2_URAMPD	(1<< 9)
#define CF_SYSTEM2_YRAMPD	(1<< 8)
#define CF_SYSTEM2_XRAMPD	(1<< 7)
#define CF_SYSTEM2_UNUSED	(1<< 5)
#define CF_SYSTEM2_XTALOFF	(1<< 4)
#define CF_SYSTEM2_ROMD		(1<< 2)
#define CF_SYSTEM2_RAMD		(1<< 0)

#define CF_SYSTEM2_ROMD_MASK	(1<<CF_SYSTEM2_ROMD_B)
#define CF_SYSTEM2_RAMD_MASK	(1<<CF_SYSTEM2_RAMD_B)


#define CF_IRAMWR 0xFC2A
#define CF_IRAMWR_REG_BITS 13

#define CF_IRAMWR_WRHDIS_B      12
#define CF_IRAMWR_ST_B           4
#define CF_IRAMWR_ENA_B          0

#define CF_IRAMWR_WRHDIS        (1<<12)
#define CF_IRAMWR_ST            (1<< 4)
#define CF_IRAMWR_ENA           (1<< 0)

#define CF_IRAMWR_ST_MASK	(0xF<<CF_IRAMWR_ST_B)
#define CF_IRAMWR_ENA_MASK	(0xF<<CF_IRAMWR_ENA_B)

  

/* SPI peripherals */

#define SPI0_CF         0xFC40
#define SPI0_CF_REG_BITS    15
#define SPI0_CLKCF      0xFC41
#define SPI0_CLKCF_REG_BITS 10
#define SPI0_STATUS     0xFC42
#define SPI0_STATUS_REG_BITS 8
#define SPI0_DATA       0xFC43
#define SPI0_FSYNC      0xFC44
#define SPI0_DEFAULT    0xFC45

#define SPI_CF_SINT_B        14
#define SPI_CF_SOMODE_B      13
#define SPI_CF_EARLYINT_B    12    // Interrupt when !SPI_ST_TXFULL
#define SPI_CF_SRESET_B      11    // software reset
#define SPI_CF_RXFIFOMODE_B  10    // int mode
#define SPI_CF_RXFIFO_ENA_B   9
#define SPI_CF_TXFIFO_ENA_B   8
#define SPI_CF_XCSMODE_B      6
#define SPI_CF_MASTER_B       5
#define SPI_CF_DLEN_B         1
#define SPI_CF_FSIDLE_B       0

#define SPI_CF_SINT        (1<<14)
#define SPI_CF_SOMODE      (1<<13)
#define SPI_CF_EARLYINT    (1<<12)    // Interrupt when !SPI_ST_TXFULL
#define SPI_CF_SRESET      (1<<11)    // software reset
#define SPI_CF_RXFIFOMODE  (1<<10)    // int mode
#define SPI_CF_RXFIFO_ENA   (1<<9)
#define SPI_CF_TXFIFO_ENA   (1<<8)
#define SPI_CF_XCSMODE      (1<<6)
#define SPI_CF_INTXCS       (0<<6)
#define SPI_CF_FALLXCS      (2<<6)
#define SPI_CF_RISEXCS      (3<<6)
#define SPI_CF_MASTER       (1<<5)
#define SPI_CF_SLAVE        (0<<5)
#define SPI_CF_DLEN         (1<<1)
#define SPI_CF_DLEN8        (7<<1)
#define SPI_CF_DLEN16      (15<<1)
#define SPI_CF_FSIDLE       (1<<0)
#define SPI_CF_FSIDLE1      (1<<0)
#define SPI_CF_FSIDLE0      (0<<0)

#define SPI_CC_CLKDIV_B       2
#define SPI_CC_INV_CLKPOL_B   1
#define SPI_CC_INV_CLKPHASE_B 0

#define SPI_CC_CLKDIV       (1<<2)
#define SPI_CC_CLKDIV_MASK  (255<<SPI_CC_CLKDIV_B)
#define SPI_CC_INV_CLKPOL   (1<<1)
#define SPI_CC_INV_CLKPHASE (1<<0)

#define SPI_ST_RXFIFOFULL_B   7
#define SPI_ST_TXFIFOFULL_B   6
#define SPI_ST_BREAK_B        5
#define SPI_ST_RXORUN_B       4
#define SPI_ST_RXFULL_B       3
#define SPI_ST_TXFULL_B       2
#define SPI_ST_TXRUNNING_B    1
#define SPI_ST_TXURUN_B       0

#define SPI_ST_RXFIFOFULL   (1<<7)
#define SPI_ST_TXFIFOFULL   (1<<6)
#define SPI_ST_BREAK        (1<<5)
#define SPI_ST_RXORUN       (1<<4)
#define SPI_ST_RXFULL       (1<<3)
#define SPI_ST_TXFULL       (1<<2)
#define SPI_ST_TXRUNNING    (1<<1)
#define SPI_ST_TXURUN       (1<<0)




/* SD card interface */

#define SD_DBG         0xFC68
#define SD_IST         0xFC6C
#define SD_IST_REG_BITS 15
#define SD_PTR         0xFC7C
#define SD_PTR_REG_BITS 12
#define SD_LEN         0xFC7D
#define SD_LEN_REG_BITS 13
#define SD_CF          0xFC7E
#define SD_ST          0xFC7F
#define SD_ST_REG_BITS  13


#define SD_DBG_ADDR_B   12
#define SD_DBG_UNUSED_B  0
  
#define SD_DBG_ADDR   (1<<12)
#define SD_DBG_UNUSED (1<< 0)


#define SD_IST_INT_ENA_B   14
#define SD_IST_UNUSED2_B    6
#define SD_IST_INT_B        5
#define SD_IST_UNUSED1_B    0

#define SD_IST_INT_ENA   (1<<14)
#define SD_IST_UNUSED2   (1<< 6)
#define SD_IST_INT       (1<< 5)
#define SD_IST_UNUSED1   (1<< 0)


#define SD_CF_NOCRCTX_B  12
#define SD_CF_NOCRCRST_B 11
#define SD_CF_4BIT_B     10
#define SD_CF_ENA_B       7
#define SD_CF_READSEL_B   6
#define SD_CF_CMDSEL_B    5
#define SD_CF_NOSTARTB_B  4
#define SD_CF_NOSTOPB_B   3
#define SD_CF_CRC16_B     2
#define SD_CF_CRC7_B      1
#define SD_CF_POLL_B      0

#define SD_CF_NOCRCTX  (1<<12)
#define SD_CF_NOCRCRST (1<<11)
#define SD_CF_4BIT     (1<<10)
#define SD_CF_ENA      (1<< 7)
#define SD_CF_READSEL  (1<< 6)
#define SD_CF_WRITESEL (0<< 6)
#define SD_CF_CMDSEL   (1<< 5)
#define SD_CF_DATASEL  (0<< 5)
#define SD_CF_NOSTARTB (1<< 4)
#define SD_CF_NOSTOPB  (1<< 3)
#define SD_CF_CRC16    (1<< 2)
#define SD_CF_CRC7     (1<< 1)
#define SD_CF_POLL     (1<< 0)

#define SD_ST_WAITSTATES_B 8
#define SD_ST_REPEAT_B     7
#define SD_ST_UNUSED_B     6
#define SD_ST_CMDBRK_B     5
#define SD_ST_DAT0_B       4
#define SD_ST_NOSTOPB_B    3
#define SD_ST_CRC16_B      2
#define SD_ST_CRC7_B       1
#define SD_ST_NOSTARTB_B   0

#define SD_ST_WAITSTATES   (1<<8)
#define SD_ST_WAITSTATES_MASK   (0x1f<<SD_ST_WAITSTATES_B)
#define SD_ST_REPEAT       (1<<7)
#define SD_ST_UNUSED       (1<<6)
#define SD_ST_CMDBRK       (1<<5)
#define SD_ST_DAT0         (1<<4)
#define SD_ST_NOSTOPB_ERR  (1<<3)
#define SD_ST_CRC16_ERR    (1<<2)
#define SD_ST_CRC7_ERR     (1<<1)
#define SD_ST_NOSTARTB_ERR (1<<0)

#define SD_ST_ANY_ERR (SD_ST_NOSTOPB_ERR|SD_ST_CRC16_ERR|SD_ST_CRC7_ERR|SD_ST_NOSTARTB_ERR)



/* Interruptable general purpose IO port 0 */

#define GPIO0_DDR 	  0xFCA0
#define GPIO0_ODATA 	  0xFCA1
#define GPIO0_IDATA 	  0xFCA2
#define GPIO0_INT_FALL 	  0xFCA3
#define GPIO0_INT_RISE 	  0xFCA4
#define GPIO0_INT_PEND 	  0xFCA5
#define GPIO0_SET_MASK 	  0xFCA6
#define GPIO0_CLEAR_MASK  0xFCA7
#define GPIO0_BIT_CONF    0xFCA8

#define GPIO_BE_DAT1_B 12
#define GPIO_BE_IO1_B   8
#define GPIO_BE_DAT0_B  4
#define GPIO_BE_IO0_B   0

#define GPIO_BE_DAT1 (1<<12)
#define GPIO_BE_IO1  (1<< 8)
#define GPIO_BE_DAT0 (1<< 4)
#define GPIO_BE_IO0  (1<< 0)

#define GPIO0_BIT_ENG0    0xFCA9
#define GPIO0_BIT_ENG1    0xFCAA





/* UART peripherals */

#define UART_IRDIV	0xFC31

#define UART_IRDIV_ENA_B 15
#define UART_IRDIV_D_B    0

#define UART_IRDIV_ENA (1<<15)
#define UART_IRDIV_D   (1<< 0)

#define UART_IRHLEN	0xFC32
#define UART_IRHLEN_REG_BITS 14

#define UART0_STATUS	0xFCC0

#define UART_ST_DLEN_B       10
#define UART_ST_IRMODE_B      8
#define UART_ST_RXRUNNING_B   5
#define UART_ST_FRAMERR_B     4
#define UART_ST_RXORUN_B      3
#define UART_ST_RXFULL_B      2
#define UART_ST_TXFULL_B      1
#define UART_ST_TXRUNNING_B   0

#define UART_ST_DLEN      (1<<10)
#define UART_ST_IRMODE    (1<< 8)
#define UART_ST_RXRUNNING (1<< 5)
#define UART_ST_FRAMERR   (1<< 4)
#define UART_ST_RXORUN    (1<< 3)
#define UART_ST_RXFULL    (1<< 2)
#define UART_ST_TXFULL    (1<< 1)
#define UART_ST_TXRUNNING (1<< 0)

#define UART0_DATA	0xFCC1
#define UART0_DATA_REG_BITS 8
#define UART0_DATAH 	0xFCC2
#define UART0_DIV	0xFCC3

#define UART_DIV_D1_B 8
#define UART_DIV_D2_B 0

#define UART_DIV_D1 (1<<8)
#define UART_DIV_D2 (1<<0)

#define UART_DIV_D1_MASK (255<<UART_DIV_D1_B)
#define UART_DIV_D2_MASK (255<<UART_DIV_D2_B)

#define UART0_TXDIV	0xFCC4

#define UART_TXDIV_D1_B 8
#define UART_TXDIV_D2_B 0

#define UART_TXDIV_D1 (1<<8)
#define UART_TXDIV_D2 (1<<0)

#define UART_TXDIV_D1_MASK (255<<UART_TXDIV_D1_B)
#define UART_TXDIV_D2_MASK (255<<UART_TXDIV_D2_B)

#define UART0_PRE	0xFCC5
#define UART0_PRE_REG_BITS 7

#define UART_PRE_PLLSW_B 6
#define UART_PRE_AUTO_B  5
#define UART_PRE_ENA_B   4
#define UART_PRE_DIV_B   0

#define UART_PRE_PLLSW (1<<6)
#define UART_PRE_AUTO  (1<<5)
#define UART_PRE_ENA   (1<<4)
#define UART_PRE_DIV   (1<<0)


#define UARTRV_STATUS	0xFCC8
#define UARTRV_DATA	0xFCC9
#define UARTRV_DATA_REG_BITS 8
#define UARTRV_DATAH 	0xFCCA
#define UARTRV_DIV	0xFCCB
#define UARTRV_TXDIV	0xFCCC
#define UARTRV_PRE	0xFCCD
#define UARTRV_PRE_REG_BITS 7

#define UARTMUX_STATUS	0xFCD0
#define UARTMUX_DATA	0xFCD1
#define UARTMUX_DATA_REG_BITS 8
#define UARTMUX_DATAH 	0xFCD2
#define UARTMUX_DIV	0xFCD3
#define UARTMUX_TXDIV	0xFCD4
#define UARTMUX_PRE	0xFCD5
#define UARTMUX_PRE_REG_BITS 7






/* SDRAM = DDR2 interface */

#define SDRAM_CF             0xFCE0
#define SDRAM_CF_REG_BITS         4
#define SDRAM_ST             0xFCE1
#define SDRAM_CA_LO          0xFCE2
#define SDRAM_CA_LO_REG_BITS     13
#define SDRAM_CA_HI          0xFCE3
#define SDRAM_DATA_LO        0xFCE4
#define SDRAM_DATA_HI        0xFCE5
#define SDRAM_T_US_DELAY     0xFCE6
#define SDRAM_T_US_DELAY_REG_BITS 9
#define SDRAM_T_INIT         0xFCE7
#define SDRAM_T_ARF          0xFCE8
#define SDRAM_T_ARF_REG_BITS     14
#define SDRAM_T_MRD_RCD      0xFCE9
#define SDRAM_T_RFC_RP       0xFCEA
#define SDRAM_T_WTR          0xFCEB
#define SDRAM_T_WTR_REG_BITS      4
#define SDRAM_C_LAT          0xFCEC
#define SDRAM_C_LAT_REG_BITS     11
#define SDRAM_C_MANMRS       0xFCED
#define SDRAM_C_EXTRA        0xFCEE
#define SDRAM_C_EXTRA_REG_BITS    9
#define SDRAM_S_REGREAD      0xFCEF
#define SDRAM_S_REGADDR      0xFCF0
#define SDRAM_S_REGADDR_REG_BITS  8
#define SDRAM_C_DDR_PAD_CTRL 0xFCFD
#define SDRAM_C_DDR_PAD_CTRL_REG_BITS 9
#define SDRAM_C_DDR_DELAY0   0xFCFE
#define SDRAM_C_DDR_DELAY1   0xFCFF

#define SDRAM_CF_MMUENA_B     0
#define SDRAM_CF_VSMODE_B     1
#define SDRAM_CF_AXIMODE_B    2
#define SDRAM_CF_READSTATUS_B 3

#define SDRAM_CF_MMUENA     (1<<0)
#define SDRAM_CF_VSMODE     (1<<1)
#define SDRAM_CF_AXIMODE    (1<<2)
#define SDRAM_CF_READSTATUS (1<<3)

#define SDRAM_ST_INIT_DONE_B                 0
#define SDRAM_ST_TX_EMPTY_B                  1
#define SDRAM_ST_RX_32BIT_WORDS_AVAILABLE_B  2
#define SDRAM_ST_RX_32BIT_WORDS_AVAILABLE_MASK (0x1f<<SDRAM_ST_RX_32BIT_WORDS_AVAILABLE_B)
#define SDRAM_ST_TX_HALFEMPTY_B              7
#define SDRAM_ST_UNUSED_B                    8
#define SDRAM_ST_READ_FAIL_B                14
#define SDRAM_ST_WRITE_FAIL_B               15

#define SDRAM_ST_INIT_DONE                (1<< 0)
#define SDRAM_ST_TX_EMPTY                 (1<< 1)
#define SDRAM_ST_RX_32BIT_WORDS_AVAILABLE (1<< 2)
#define SDRAM_ST_TX_HALFEMPTY             (1<< 7)
#define SDRAM_ST_UNUSED                   (1<< 8)
#define SDRAM_ST_READ_FAIL                (1<<14)
#define SDRAM_ST_WRITE_FAIL               (1<<15)

#define SDRAM_CA_LO_SHORT_B      0
#define SDRAM_CA_LO_CMD_B        1
#define SDRAM_CA_LO_ADDRLO_B     3
#define SDRAM_CA_LO_ADDRLO_MASK  (0x1fff<<SDRAM_CA_LO_ADDRLO_B)

#define SDRAM_CA_LO_SHORT      (1<<0)
#define SDRAM_CA_LO_CMD        (1<<1)
#define SDRAM_CA_LO_CMD_WRITE  (3<<SDRAM_CA_LO_CMD_B)
#define SDRAM_CA_LO_CMD_READ   (2<<SDRAM_CA_LO_CMD_B)
#define SDRAM_CA_LO_ADDRLO     (1<<3)


  
#define SDRAM_T_US_DELAY1     (1<<0)


#define SDRAM_T_INIT_INIT_B      0
#define SDRAM_T_INIT_INIT_MASK   (0xff<<SDRAM_T_INIT_INIT_B)
#define SDRAM_T_INIT_INIT5_B     8
#define SDRAM_T_INIT_INIT5_MASK  (0xf<<SDRAM_T_INIT_INIT5_B)
#define SDRAM_T_INIT_ZQINIT_B   12
#define SDRAM_T_INIT_ZQINIT_MASK (0xf<<SDRAM_T_INIT_ZQINIT_B)

#define SDRAM_T_INIT_INIT   (1<< 0)
#define SDRAM_T_INIT_INIT5  (1<< 8)
#define SDRAM_T_INIT_ZQINIT (1<<12)

#define SDRAM_T_MRD_RCD_RCD_B  0
#define SDRAM_T_MRD_RCD_RCD_MASK  (0xff<<SDRAM_T_MRD_RCD_RCD_B)
#define SDRAM_T_MRD_RCD_MRD_B  8
#define SDRAM_T_MRD_RCD_MRD_MASK  (0xff<<SDRAM_T_MRD_RCD_MRD_B)

#define SDRAM_T_MRD_RCD_RCD  (1<<0)
#define SDRAM_T_MRD_RCD_MRD  (1<<8)

#define SDRAM_T_RFC_RP_RP_B   0
#define SDRAM_T_RFC_RP_RP_MASK (0xff<<SDRAM_T_RFC_RP_RP_B)
#define SDRAM_T_RFC_RP_RFC_B  8
#define SDRAM_T_RFC_RP_RFC_MASK (0xff<<SDRAM_T_RFC_RP_RFC_B)

#define SDRAM_T_RFC_RP_RP   (1<<0)
#define SDRAM_T_RFC_RP_RFC  (1<<8)

#define SDRAM_C_LAT_RD_B   0
#define SDRAM_C_LAT_RD_MASK (0xf<<SDRAM_C_LAT_RD_B)
#define SDRAM_C_LAT_WR_B   4
#define SDRAM_C_LAT_WR_MASK (0x7<<SDRAM_C_LAT_WR_B)
#define SDRAM_C_LAT_RW_B   7
#define SDRAM_C_LAT_RW_MASK (0xf<<SDRAM_C_LAT_RW_B)

#define SDRAM_C_LAT_RD   (1<<0)
#define SDRAM_C_LAT_WR   (1<<4)
#define SDRAM_C_LAT_RW   (1<<7)

#define SDRAM_C_EXTRA_CAPT_WIN_B        0
#define SDRAM_C_EXTRA_CAPT_WIN_MASK     (0xf<<SDRAM_C_EXTRA_CAPT_WIN_B)
#define SDRAM_C_EXTRA_WRITE_LAT_EXTRA_B 4
#define SDRAM_C_EXTRA_EXTRAW_DELAY_B    5
#define SDRAM_C_EXTRA_EXTRAW_DELAY_MASK (0xf<<SDRAM_C_EXTRA_EXTRAW_DELAY_B)

#define SDRAM_C_EXTRA_CAPT_WIN        (1<<0)
#define SDRAM_C_EXTRA_WRITE_LAT_EXTRA (1<<4)
#define SDRAM_C_EXTRA_EXTRAW_DELAY    (1<<5)


#define SDRAM_C_DDR_PAD_CTRL_DS_B 3
#define SDRAM_C_DDR_PAD_CTRL_DS_MASK (0x3f<<SDRAM_C_DDR_PAD_CTRL_DS_B)
#define SDRAM_C_DDR_PAD_CTRL_DA_B 0
#define SDRAM_C_DDR_PAD_CTRL_DA_MASK (0x7<<SDRAM_C_DDR_PAD_CTRL_DA_B)

#define SDRAM_C_DDR_PAD_CTRL_DS (1<<3)
#define SDRAM_C_DDR_PAD_CTRL_DA (1<<0)


/* Master clock counter */

#define MCLK_COUNTL 0xFD20
#define MCLK_COUNTH 0xFD21
#define MCLK_DIFFL  0xFD22
#define MCLK_DIFFH  0xFD23
#define MCLK_CF     0xFD24
#define MCLK_CF_REG_BITS 10

#define MCLK_CF_BEDGE_B  9
#define MCLK_CF_EDGE_B   8
#define MCLK_CF_DSEL_B   3
#define MCLK_CF_DSEL_MASK  (31<<MCLK_CF_DSEL_B)
#define MCLK_CF_UNUSED_B 1
#define MCLK_CF_DENA_B   0

#define MCLK_CF_BEDGE   (1<<9)
#define MCLK_CF_EDGE    (1<<8)
#define MCLK_CF_DSEL    (1<<3)
#define MCLK_CF_UNUSED  (1<<1)
#define MCLK_CF_DENA    (1<<0)


#define MCLK_CF_SEL_GPIO0_0     0
#define MCLK_CF_SEL_GPIO0_1     1
#define MCLK_CF_SEL_GPIO0_2     2
#define MCLK_CF_SEL_GPIO0_3     3
#define MCLK_CF_SEL_GPIO0_4     4
#define MCLK_CF_SEL_GPIO0_5     5
#define MCLK_CF_SEL_GPIO0_6     6
#define MCLK_CF_SEL_GPIO0_7     7
#define MCLK_CF_SEL_GPIO0_8     8
#define MCLK_CF_SEL_GPIO0_9     9
#define MCLK_CF_SEL_GPIO0_10   10
#define MCLK_CF_SEL_GPIO0_11   11
#define MCLK_CF_SEL_GPIO0_12   12
#define MCLK_CF_SEL_GPIO0_13   13
#define MCLK_CF_SEL_UARTRV_RX  14
#define MCLK_CF_SEL_UARTMUX_RX 15


/* Watchdog peripheral */

#define WDOG_CF         0xFE20
#define WDOG_KEY        0xFE21
#define WDOG_DUMMY      0xFE22
#define WDOG_BREAK      WDOG_DUMMY
#define WDOG_KEY_VAL    0x4ea9


/* ADC registers */

#define ADC_CF       0xFE40
#define ADC_MEMTSTDL 0xFE42
#define ADC_MEMTSTDH 0xFE43
#define ADC_SDML     0xFE44
#define ADC_SDMH     0xFE45
#define ADC_SDMH_REG_BITS 11
#define ADC_LEFTL    0xFE46
#define ADC_LEFT     0xFE47
#define ADC_RIGHTL   0xFE48
#define ADC_RIGHT    0xFE49
#define ADC_D6LEFTL  0xFE4E
#define ADC_D6LEFT   0xFE4F
#define ADC_D6RIGHTL 0xFE50
#define ADC_D6RIGHT  0xFE51
#define ADC_FLEFTL   0xFC3A
#define ADC_FLEFT    0xFC3B
#define ADC_FRIGHTL  0xFC3C
#define ADC_FRIGHT   0xFC3D
#define ADC_FADDR    0xFC3E
#define ADC_FADDR_REG_BITS 2

#define ADC_CF_MEMTST_B  15
#define ADC_CF_UNUSED_B  11
#define ADC_CF_MEMSDIV_B  9
#define ADC_CF_MEMSENA_B  8
#define ADC_CF_ADFS_B     3
#define ADC_CF_ENABLE_B   2
#define ADC_CF_DEC6ENA_B  1
#define ADC_CF_FILTENA_B  0

#define ADC_CF_MEMTST  (1<<15)
#define ADC_CF_UNUSED  (1<<11)
#define ADC_CF_MEMSDIV (1<< 9)
#define ADC_CF_MEMSENA (1<< 8)
#define ADC_CF_ADFS    (1<< 3)
#define ADC_CF_ENABLE  (1<< 2)
#define ADC_CF_DEC6ENA (1<< 1)
#define ADC_CF_FILTENA (1<< 0)

/* Bit pattern definitions */
#define ADC_CF_MEMSDIV_4  (0<<AD_CF_ADFS_B)
#define ADC_CF_MEMSDIV_6  (2<<AD_CF_ADFS_B)
#define ADC_CF_MEMSDIV_8  (1<<AD_CF_ADFS_B)
#define ADC_CF_MEMSDIV_MASK (3<<AD_CF_MEMSDIV)

/* Bit pattern definitions */
#define ADC_CF_ADFS_24K  (3<<AD_CF_ADFS_B)
#define ADC_CF_ADFS_48K  (2<<AD_CF_ADFS_B)
#define ADC_CF_ADFS_96K  (1<<AD_CF_ADFS_B)
#define ADC_CF_ADFS_192K (0<<AD_CF_ADFS_B)
#define ADC_CF_ADFS_MASK (3<<AD_CF_ADFS_B)

#define ADC_FADDR_SEL_DEC6  3
#define ADC_FADDR_SEL_SRC   2
#define ADC_FADDR_SEL_ADC   1
//#define ADC_FADDR_SEL_SRC   0 // Alternative value



/* Timer peripheral */

#define TIMER_CF 	0xfe80
#define TIMER_CF_REG_BITS   12
#define TIMER_ENA 	0xfe81
#define TIMER_ENA_REG_BITS  4
#define TIMER_T0L    	0xfe84
#define TIMER_T0H    	0xfe85
#define TIMER_T0CNTL 	0xfe86
#define TIMER_T0CNTH 	0xfe87
#define TIMER_T1L    	0xfe88
#define TIMER_T1H    	0xfe89
#define TIMER_T1CNTL 	0xfe8a
#define TIMER_T1CNTH 	0xfe8b
#define TIMER_T2L    	0xfe8c
#define TIMER_T2H    	0xfe8d
#define TIMER_T2CNTL 	0xfe8e
#define TIMER_T2CNTH 	0xfe8f

#define TIMER_ENA_CAP0_B  3
#define TIMER_ENA_T2_B	  2
#define TIMER_ENA_T1_B	  1
#define TIMER_ENA_T0_B	  0

#define TIMER_ENA_CAP0  (1<<3)
#define TIMER_ENA_T2	(1<<2)
#define TIMER_ENA_T1	(1<<1)
#define TIMER_ENA_T0	(1<<0)













/* DAC volume control */

#define DAC_VOL          0xFEC0

#define DAC_VOL_LADD_B 12   // Left channel in 0.5 dB steps
#define DAC_VOL_LADD_MASK (15<<DAC_VOL_LADD_B)
#define DAC_VOL_LSFT_B  8   // Left channel in -6 dB steps
#define DAC_VOL_LSFT_MASK (15<<DAC_VOL_LSFT_B)
#define DAC_VOL_RADD_B  4   // Right channel in 0.5 dB steps
#define DAC_VOL_RADD_MASK (15<<DAC_VOL_RADD_B)
#define DAC_VOL_RSFT_B  0   // Right channel in -6 dB steps
#define DAC_VOL_RSFT_MASK (15<<DAC_VOL_RSFT_B)

#define DAC_VOL_LADD (1<<12)   // Left channel in 0.5 dB steps
#define DAC_VOL_LSFT (1<< 8)   // Left channel in -6 dB steps
#define DAC_VOL_RADD (1<< 4)   // Right channel in 0.5 dB steps
#define DAC_VOL_RSFT (1<< 0)   // Right channel in -6 dB steps



/* DAC offset registers */

#define DAOSET_CF        0xFEC1
#define DAOSET_CF_REG_BITS 15
#define DAOSET_LEFT_LSB	 0xFEC2
#define DAOSET_LEFT   	 0xFEC3
#define DAOSET_RIGHT_LSB 0xFEC4
#define DAOSET_RIGHT     0xFEC5

#define DAOSET_CF_URUN_B 14
#define DAOSET_CF_FULL_B 13
#define DAOSET_CF_ENA_B  12
#define DAOSET_CF_FS_B    0	// 12 bits

#define DAOSET_CF_URUN (1<<14)
#define DAOSET_CF_FULL (1<<13)
#define DAOSET_CF_ENA  (1<<12)
#define DAOSET_CF_FS   (1<< 0)	// 12 bits

#define DAOSET_CF_FS_MASK (0x0FFF<<DAOSET_CF_FS_B)


/* Sample rate converter (SRC) registers */

#define SRC_CF   	 0xFECA
#define SRC_LEFT_LSB   	 0xFEC6
#define SRC_LEFT   	 0xFEC7
#define SRC_RIGHT_LSB  	 0xFEC8
#define SRC_RIGHT   	 0xFEC9

#define SRC_CF_ORUN_B  15
#define SRC_CF_RFULL_B 14
#define SRC_CF_LFULL_B 13
#define SRC_CF_ENA_B   12
#define SRC_CF_FS_B     0	// 12 bits

#define SRC_CF_ORUN  (1<<15)
#define SRC_CF_RFULL (1<<14)
#define SRC_CF_LFULL (1<<13)
#define SRC_CF_ENA   (1<<12)
#define SRC_CF_FS    (1<< 0)	// 12 bits



/* Analog control registers */

#define ANA_CF0          0xfecb
#define ANA_CF0_REG_BITS 14

#define ANA_CF0_ADCOFF_B   13
#define ANA_CF0_XTDIV_B    12
#define ANA_CF0_ANA_ENA_B   4
#define ANA_CF0_ADC2_ENA_B  3
#define ANA_CF0_ADC1_ENA_B  2
#define ANA_CF0_DAC_ENA_B   1
#define ANA_CF0_REF_ENA_B   0

#define ANA_CF0_ADCOFF   (1<<13)
#define ANA_CF0_XTDIV    (1<<12)
#define ANA_CF0_ANA_ENA  (1<< 4)
#define ANA_CF0_ADC2_ENA (1<< 3)
#define ANA_CF0_ADC1_ENA (1<< 2)
#define ANA_CF0_DAC_ENA  (1<< 1)
#define ANA_CF0_REF_ENA  (1<< 0)


#define ANA_CF1          0xfecc
#define ANA_CF1_REG_BITS 14

#define ANA_CF1_LCKST_B    13
#define ANA_CF1_LCKIKI_B   12
#define ANA_CF1_UENA_B      8
#define ANA_CF1_UTM_ENA_B   7
#define ANA_CF1_2G_ENA_B    6
#define ANA_CF1_480_ENA_B   5
#define ANA_CF1_UTMBIAS_B   4
#define ANA_CF1_2GCENTR_B   0

#define ANA_CF1_LCKST   (13<<1)
#define ANA_CF1_LCKIKI  (12<<1)
#define ANA_CF1_UENA    ( 8<<1)
#define ANA_CF1_UTM_ENA ( 7<<1)
#define ANA_CF1_2G_ENA  ( 6<<1)
#define ANA_CF1_480_ENA ( 5<<1)
#define ANA_CF1_UTMBIAS ( 4<<1)
#define ANA_CF1_2GCENTR ( 0<<1)


#define ANA_CF2          0xFED2

#define ANA_CF2_IN_B    12
#define ANA_CF2_UNUSED   0


#define ANA_CF3          0xFED3

#define ANA_CF3_UNUSED   0


#define DAC_MODE          0xFED7
#define DAC_MODE_REG_BITS 11

#define DAC_MODE_ENA_96K_B  10 /* change samplerate control scaling */
#define DAC_MODE_SRCXYDIV_B  0

#define DAC_MODE_ENA_96K  (1<<10) /* change samplerate control scaling */
#define DAC_MODE_SRCXYDIV (1<< 0)

#define DAC_MTST          0xFECF
#define ANA_ADJUST        0xFED1

#define DAC_SRCL         0xFC34    // 15:0 = SRC bits 15: 0
#define DAC_SRCH         0xFC35    //  3:0 = SRC bits 19:16
#define DAC_LEFTL        0xFC36    // 15:8 = DAC bits  7: 0
#define DAC_LEFT         0xFC37    // 15:0 = DAC bits 24: 8
#define DAC_RIGHTL       0xFC38    // 15:8 = DAC bits  7: 0
#define DAC_RIGHT        0xFC39    // 15:0 = DAC bits 24: 8




#ifdef ASM

#ifndef STP
#  ifdef PERIP_IN_X
/* Also defined in rtosdefs.h, don't collide with that. */
#    define STP stx
#    define LDP ldx
#    define STNP sty
#    define LDNP ldy
#  else
/* Also defined in rtosdefs.h, don't collide with that. */
#    define STP sty
#    define LDP ldy
#    define STNP stx
#    define LDNP ldx
#  endif
#endif

#else /* !ASM */

#ifdef PERIP_IN_X
#  define PERIP(a) USEX(a)
#  define PERIP32(a) (*(volatile u_int32 *)(u_int16)(a))
#else
#  define PERIP(a) USEY(a)
#  define PERIP32(a) (*(__mem_y volatile u_int32 *)(u_int16)(a))
#endif

/*
  SpiLoadLong() does not return!
   m24 = 0 for 16-bit SPI EEPROM address.
   m24 > 0 for 24-bit SPI EEPROM address.
   m24 < 0 for 32-bit SPI EEPROM address.
 */
void SpiLoadLong(register __reg_a u_int32 startAddr, register __i0 s_int16 m24);
void SpiDelay(register __a0 u_int16 wait);
auto u_int16 SpiSendReceive(register __a0 u_int16 data);

void Restart(void);

#endif /*!ASM*/

#endif /*__VSRV_H__*/
