VSRV: Simple 32-bit Linux-capable RISC-V cores

VSRV is an open-source processor family developed by VLSI Solution Oy, featuring two generations of energy-efficient 32-bit RISC-V cores. Designed for embedded systems and IoT devices, these cores provide a robust platform for standard networking stacks and modern software ecosystems. The cores are licensed under Solderpad Hardware License v2.

Background and Evolution

The VSRV project originated from an evaluation of the scalar UltraEmbedded RISC-V core. While the original implementation was one of the simplest cores capable of booting Linux, it had architectural and structural limitations, such as the absence of a data cache, which resulted in significantly long boot times and limited support for newer Linux kernels.

VLSI Solution addressed these limitations by completely rewriting the implementation into a uniform VHDL environment to improve maintainability and integration and introducing significant enhancements, resulting in the VSRV1 and VSRV2 cores.

VSRV1 established the baseline architecture as a simple, single-issue, in-order 5-stage RV32IM core capable of running a full Linux operating system at low clock frequencies. Key architectural improvements included the addition of a data cache, extension of the MMU for larger memory support, simplification of the AXI interface for lower latency, and introduction of a lightweight VSBUS peripheral interface. These changes resulted in a clean, area-efficient, and configurable Linux-capable processor architecture.

VSRV2 builds directly on the foundation of VSRV1 and focuses on improving memory performance, data movement, and computational efficiency. The AXI interface was widened from 32 bits to 64 bits to increase memory bandwidth, and multiple DMA engines were introduced to offload data transfers. A boot ROM was added to enable faster and more autonomous system startup. In addition, several RISC-V ISA extensions, including atomic operations and bit-manipulation extensions, were implemented to improve execution efficiency for software workloads and decrease the boot time.

Architecture Overview

Both CPU generations are based on a 5-stage in-order pipeline architecture. They support the RV32IM instruction set and include the mandatory Memory Management Unit (MMU) required to run a standard Linux kernel.

Repositories and Test chips