VSRV: A 32-bit RISC-V Linux-Capable Core

Goal: A Simple 32-bit Linux-Capable RISC-V Processor Core

The goal of the VSRV project is to create a simple 32-bit RISC-V ISA CPU core capable of running current Linux. From the application point of view the VSRV is between the RISC-V microcontrollers and the high performance cores. The clear advantage over the microcontrollers is that it supports all features necessary for running the Linux operating system. Practically no custom software effort is needed to support complex interface protocols (such as ethernet) which have many layers of software.

The project is done under the Tristan project and funded by the European Union and Business Finland. The first published core (VSRV1) supports all mandatory hardware and peripherals to run the Linux 6.1 kernel.

Core

Published

Core Features

Peripherals

Link

VSRV1

2025-01-28

RV32IMSU zicsr zifensei

GPIO, UART, SPI, Timer, PLIC

here

Test Chip

Test chip of VSRV1 core is available here

 

 

TRISTAN Project has received funding from the Chips Joint Undertaking (Chips-JU) under the grant agreement nr. 101095947. Chips-JU receives support from the European Union’s Horizon Europe’s research and innovation programme and Austria, Belgium, Bulgaria, Croatia, Cyprus, Czechia, Germany, Denmark, Estonia, Greece, Spain, Finland, France, Hungary, Ireland, Israel, Iceland, Italy, Lithuania, Luxembourg, Latvia, Malta, Netherlands, Norway, Poland, Portugal, Romania, Sweden, Slovenia, Slovakia and Turkey.