ASIC Design and Manufacturing Services

Survey of the requirements

A typical starting point of an ASIC project is that a customer wants to estimate the benefits of using an ASIC in their next generation product.

The customer rarely knows the whole spectrum of ASIC possibilities and what technology would be the most suited for his technical and commercial requirements. Therefore, our first step is to discuss with the customer and try to understand the target product and business plans.

The technical and business survey may lead us to propose an ASIC project. Typically, when a product requires low power consumption, has mixed signal processing requirements and an annual volume above 100k for 3-5 years, then ASIC is the most competitive solution. In industrial applications, annual volumes can be lower (30k) since the product life time is typically much longer (in the range of 10 years).

ASIC Design


The first step of the project is to create and agree on a specification for the design including functional blocks, the package and any special requirements. When the specification is clear enough, we are able to make a quote for the development project up to engineering samples and a budgetary quote for the remaining steps as well as the unit price of the ASIC device.

Design and Verification

Whenever possible, we try to make a breadboard of the system prior to going to silicon. The objective is to verify that the design works in its real environment. It also gives a platform for the firmware development. The breadboard usually consists of a PCB with one or more FPGA devices, our analog test ICs and other components as required. This way we minimize the risk of a system level error.


At this stage, we will put everything together. Analog, RF and memory components are put to the top layout as functional blocks. They have been verified by circuit simulation. The digital part uses the same VHDL that has been functionally verified using an FPGA. The VHDL is synthesized to a netlist of gates that is further converted to a layout by using timing driven placement and standard cell routing. The logic uses our in-house low power standard cell library of the target technology. Peripheral cells are added and optimally positioned for the target package. Finally, top level routing is done to connect the interfacing signals and power between the blocks and peripheral cells. When layout is complete, we use Check List to systematically go through a long list of final verifications.



Once the design has passed the layout design review, the geometrical layout data is converted to GDSII format, encrypted, and uploaded to the wafer manufacturer to participate in the Multi Project Wafer (MPW) run of the foundry. The idea of the MPW is to make prototypes for many customers by using the same wafers and thereby share the mask and wafer costs between many clients.

The manufacturing of the MPW wafers usually takes about 6 weeks. The engineering samples are shipped as backgrinded dies from the wafer manufacturer to protect the IP rights of multiple customers sharing the same wafers. The dies are sent to our assembly and test subcontractor that will package the dies. The untested engineering samples are then shipped to us for evaluation.

Evaluation of the Engineering Samples

During the several weeks of waiting time of the wafer and assembly manufacturing, we prepare an Evaluation Board for the engineering samples. The purpose of the Evaluation Board is to provide full access with available laboratory equipment to debug the functionality and performance of the device. The customer is usually preparing a second board to evaluate the device in the end product.

Transfer to Production

Mask Generation

Once engineering samples have been evaluated by the customer, the layout is fine tuned based on the non-conforming findings of the MPW. The final layout is again converted to GDSII format, encrypted and uploaded to the mask manufacturer. Masks are the photographic plates used in the foundry manufacturing process to create the circuit layer by layer. A typical CMOS process requires 19 - 24 masks.

Manufacturing of the Prototype Wafers

The next step is that the silicon foundry manufactures so-called corner wafers for qualification. Our approach is usually to start one engineering lot of 12 wafers that consists of two sublots, each having six corner wafers. The second sublot is put on hold when the lot reaches the first metal layer of the wafer process for possible Engineering Change Order (ECO) later.

Assembly of the Prototype Wafers

The engineering wafers are shipped to the Assembly and Test subcontractor that will back grind the wafers to suitable thickness, saw them into dies, attach and wire bond them on the leadframe, and finally encapsulate them in plastic. The untested engineering samples are shipped to us for evaluation.

Evaluation of the Prototypes

The prototypes are evaluated with the same setup as the engineering samples to confirm the effectiveness of the fixes and enhancements.

Final Test

During the several weeks of waiting the wafer and assembly manufacturing, we prepare the Final Test setup for the device. Once we have the preliminary test program, the loadboard, and the sockets for the handler, and golden samples of prototypes from our laboratory, we will travel to our assembly and test subcontractor and debug the Final Test and Qualification programs for the device.


When Final Test for the device has been released, we will start qualification. It consists of three major subclasses: Package, Device and Process capability. You can read more about the test here. Once qualification has passed the device is ready for volume production.

Volume Production

The volume production stage is very simple to the customer: they only need to send their forecast and POs. We will take care of the rest.

Among our production activities the most important are Material Control and Product Engineering.

Material Control is the interface to the customer and our subcontractors. The main functions are forecasts, purchase orders, resource planning, priority list, subcontracting and shipments.

Product Engineering is the technical interface to the customer. They will answer the technical questions, do failure analysis of non-conforming products, and work with the statistics of the test results on a daily basis in order to improve the product quality and yield.

Cost Discussion

Processor, peripherals and memory

The cost of an ASIC project depends on the complexity of the device. High complexity requires manufacturing technologies that increases the NRE of the project. The amount of on-chip RAM memory and the speed of the processor are typically the main parameters for technology selection. The following table gives some hints of the achievable performance for low power applications.


On-chip RAM (note 1)

Speed of the signal processor (note 2)

0.35 um

200 kbit

25 MHz

0.25 um

500 kbit

55 MHz

0.18 um

1000 kbit

100 MHz

0.13 um

2000 kbit

150 MHz

Note 1: Upper limit for single cycle fast memory
Note 2: Multiple core option can multiply the effective speed.


Older 0.5 um and 0.35 um technologies are beneficial when high SNR is required because they provide higher signal levels than modern technologies due to a higher maximum operating voltage. Some modern 0.18 um technologies can provide a high voltage analog option to overcome this limitation.


RF is favoring newest technologies since fT increases by decreasing the transistor minimum gate length. Also inductors and power routing benefit the decreased metal pitch and copper material of the newest technologies.


A simple audio processing circuit that has an audio ADC and DAC, some peripherals such as I2C and hardwired logic for some fixed signal processing functions would be a small device and would likely be implemented by using 0.35 um technology. NRE would be in range of 150 kUSD and estimated unit price in range of 0.7-1.0 USD for 100k/year quantity and 0.5-0.7 USD for 1M/year quantity.

A single-chip walkie talkie phone containing an RF transmitter and receiver, an ADC, a DAC, a speaker interface, regulators, a DSP processor, 0.5Mbit RAM, a flash, display and key interfaces, could be implemented by using 0.18 um technology. NRE would be in range of 300 kUSD and estimated unit price in range of 2 USD for 100k/year quantity and 1.5 USD for 1M/year quantity.

Both examples assume full turn-key service.